📄 cnt4.rpp.talkback.xml
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<!--
This XML file (created on Fri Mar 21 17:40:58 2008) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature. To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder. For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_176.xsd</schema><license>
<host_id>000cf1496c62</host_id>
<nic_id>000cf1496c62</nic_id>
<cdrive_id>38441af0</cdrive_id>
</license>
<tool>
<name>Quartus II</name>
<version>5.1</version>
<build>Build 176</build>
<binary_type>32</binary_type>
<module>quartus_rpp.exe</module>
<edition>Web Edition</edition>
<compilation_end_time>Fri Mar 21 17:40:58 2008</compilation_end_time>
</tool>
<machine>
<os>Windows XP</os>
<cpu>
<proc_count>1</proc_count>
<cpu_freq units="MHz">1399</cpu_freq>
</cpu>
<ram units="MB">751</ram>
</machine>
<top_file>E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/cnt4</top_file>
<mep_data>
<command_line>quartus_rpp cnt4 -c cnt4 --netlist_type=sgate</command_line>
</mep_data>
<software_data>
<smart_recompile>off</smart_recompile>
</software_data>
<messages>
<info>Info: Quartus II RTL Viewer, Technology Map Viewer & State Machine Viewer Preprocessor was successful. 0 errors, 0 warnings</info>
<info>Info: Elapsed time: 00:00:01</info>
<info>Info: Processing ended: Fri Mar 21 17:40:58 2008</info>
<info>Info: Command: quartus_rpp cnt4 -c cnt4 --netlist_type=sgate</info>
<info>Info: Running Quartus II RTL Viewer, Technology Map Viewer & State Machine Viewer Preprocessor</info>
</messages>
<fitter_settings>
<row>
<option>Device</option>
<setting>AUTO</setting>
</row>
<row>
<option>Use smart compilation</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Optimize Timing</option>
<setting>Normal compilation</setting>
<default_value>Normal compilation</default_value>
</row>
<row>
<option>Optimize IOC Register Placement for Timing</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Limit to One Fitting Attempt</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Fitter Initial Placement Seed</option>
<setting>1</setting>
<default_value>1</default_value>
</row>
<row>
<option>Slow Slew Rate</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Fitter Effort</option>
<setting>Auto Fit</setting>
<default_value>Auto Fit</default_value>
</row>
</fitter_settings>
<fitter_device_options>
<row>
<option>Enable user-supplied start-up clock (CLKUSR)</option>
<setting>Off</setting>
</row>
<row>
<option>Enable device-wide reset (DEV_CLRn)</option>
<setting>Off</setting>
</row>
<row>
<option>Enable device-wide output enable (DEV_OE)</option>
<setting>Off</setting>
</row>
<row>
<option>Enable INIT_DONE output</option>
<setting>Off</setting>
</row>
<row>
<option>Configuration scheme</option>
<setting>Passive Serial</setting>
</row>
<row>
<option>Reserve all unused pins</option>
<setting>As output driving an unspecified signal</setting>
</row>
<row>
<option>Security bit</option>
<setting>Off</setting>
</row>
<row>
<option>Base pin-out file on sameframe device</option>
<setting>Off</setting>
</row>
</fitter_device_options>
<analysis___synthesis_settings>
<row>
<option>Top-level entity name</option>
<setting>cnt4</setting>
<default_value>cnt4</default_value>
</row>
<row>
<option>Family name</option>
<setting>MAX7000S</setting>
<default_value>Stratix</default_value>
</row>
<row>
<option>Use smart compilation</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Create Debugging Nodes for IP Cores</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Preserve fewer node names</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Disable OpenCore Plus hardware evaluation</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Verilog Version</option>
<setting>Verilog_2001</setting>
<default_value>Verilog_2001</default_value>
</row>
<row>
<option>VHDL Version</option>
<setting>VHDL93</setting>
<default_value>VHDL93</default_value>
</row>
<row>
<option>State Machine Processing</option>
<setting>Auto</setting>
<default_value>Auto</default_value>
</row>
<row>
<option>Extract Verilog State Machines</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Extract VHDL State Machines</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Add Pass-Through Logic to Inferred RAMs</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>NOT Gate Push-Back</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Power-Up Don't Care</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Remove Redundant Logic Cells</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Remove Duplicate Registers</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Ignore CARRY Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore CASCADE Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore GLOBAL Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore ROW GLOBAL Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A</option>
<setting>Auto</setting>
<default_value>Auto</default_value>
</row>
<row>
<option>Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Limit AHDL Integers to 32 Bits</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A</option>
<setting>Speed</setting>
<default_value>Speed</default_value>
</row>
<row>
<option>Allow XOR Gate Usage</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Logic Cell Insertion</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A</option>
<setting>4</setting>
<default_value>4</default_value>
</row>
<row>
<option>Auto Parallel Expanders</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Open-Drain Pins</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Remove Duplicate Logic</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Resource Sharing</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A</option>
<setting>100</setting>
<default_value>100</default_value>
</row>
<row>
<option>Ignore translate_off and translate_on Synthesis Directives</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Show Parameter Settings Tables in Synthesis Report</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>HDL message level</option>
<setting>Level2</setting>
<default_value>Level2</default_value>
</row>
</analysis___synthesis_settings>
<assembler_settings>
<row>
<option>Use smart compilation</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Generate Serial Vector Format File (.svf) for Target Device</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Generate a JEDEC STAPL Format File (.jam) for Target Device</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Generate an uncompressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Compression mode</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Clock source for configuration device</option>
<setting>Internal</setting>
<default_value>Internal</default_value>
</row>
<row>
<option>Clock frequency of the configuration device</option>
<setting units="MHz">10</setting>
<default_value units="MHz">10</default_value>
</row>
<row>
<option>Divide clock frequency by</option>
<setting>1</setting>
<default_value>1</default_value>
</row>
<row>
<option>JTAG user code for target device</option>
<setting>Ffff</setting>
<default_value>Ffff</default_value>
</row>
<row>
<option>Auto user code</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Security bit</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Configuration device auto user code</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Generate Tabular Text File (.ttf) For Target Device</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Generate Raw Binary File (.rbf) For Target Device</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Hexadecimal Output File start address</option>
<setting>0</setting>
<default_value>0</default_value>
</row>
<row>
<option>Hexadecimal Output File count direction</option>
<setting>Up</setting>
<default_value>Up</default_value>
</row>
</assembler_settings>
<clock_settings_summary>
<row>
<clock_node_name>CLK</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
</clock_settings_summary>
<input_pins>
<row>
<name>CLK</name>
<pin__>43</pin__>
<combinational_fan_out>4</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>yes</global>
<input_register>no</input_register>
<i_o_standard>TTL</i_o_standard>
<location_assigned_by>Fitter</location_assigned_by>
</row>
</input_pins>
<output_pins>
<row>
<name>Q[0]</name>
<pin__>4</pin__>
<lab>1</lab>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>TTL</i_o_standard>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>Q[1]</name>
<pin__>5</pin__>
<lab>1</lab>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>TTL</i_o_standard>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>Q[2]</name>
<pin__>6</pin__>
<lab>1</lab>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>TTL</i_o_standard>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>Q[3]</name>
<pin__>8</pin__>
<lab>1</lab>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>TTL</i_o_standard>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
</output_pins>
</talkback>
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