ddsc.fit.rpt

DDS数字频率合成器

; Optimize Hold Timing                                   ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                            ; Off                            ; Off                            ;
; PowerPlay Power Optimization                           ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                        ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing             ; On                             ; On                             ;
; Limit to One Fitting Attempt                           ; Off                            ; Off                            ;
; Final Placement Optimizations                          ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations            ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                          ; 1                              ; 1                              ;
; PCI I/O                                                ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                  ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                              ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                     ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/III/Cyclone II/III ; Auto                           ; Auto                           ;
; Auto Delay Chains                                      ; On                             ; On                             ;
; Auto Merge PLLs                                        ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                      ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic     ; Off                            ; Off                            ;
; Perform Register Duplication                           ; Off                            ; Off                            ;
; Perform Register Retiming                              ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                 ; Off                            ; Off                            ;
; Fitter Effort                                          ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                        ; Normal                         ; Normal                         ;
; Auto Global Clock                                      ; On                             ; On                             ;
; Auto Global Register Control Signals                   ; On                             ; On                             ;
; Stop After Congestion Map Generation                   ; Off                            ; Off                            ;
; Use smart compilation                                  ; Off                            ; Off                            ;
+--------------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/毕业设计/dds/ddsc.pin.


+------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                          ;
+---------------------------------------------+--------------------------+
; Resource                                    ; Usage                    ;
+---------------------------------------------+--------------------------+
; Total logic elements                        ; 32 / 18,752 ( < 1 % )    ;
;     -- Combinational with no register       ; 0                        ;
;     -- Register only                        ; 0                        ;
;     -- Combinational with a register        ; 32                       ;
;                                             ;                          ;
; Logic element usage by number of LUT inputs ;                          ;
;     -- 4 input functions                    ; 0                        ;
;     -- 3 input functions                    ; 31                       ;
;     -- <=2 input functions                  ; 1                        ;
;     -- Register only                        ; 0                        ;
;                                             ;                          ;
; Logic elements by mode                      ;                          ;
;     -- normal mode                          ; 1                        ;
;     -- arithmetic mode                      ; 31                       ;
;                                             ;                          ;
; Total registers*                            ; 32 / 19,130 ( < 1 % )    ;
;     -- Dedicated logic registers            ; 32 / 18,752 ( < 1 % )    ;
;     -- I/O registers                        ; 0 / 378 ( 0 % )          ;
;                                             ;                          ;
; Total LABs:  partially or completely used   ; 2 / 1,172 ( < 1 % )      ;
; User inserted logic elements                ; 0                        ;
; Virtual pins                                ; 0                        ;
; I/O pins                                    ; 43 / 142 ( 30 % )        ;
;     -- Clock pins                           ; 2 / 8 ( 25 % )           ;
; Global signals                              ; 1                        ;
; M4Ks                                        ; 3 / 52 ( 6 % )           ;
; Total memory bits                           ; 10,240 / 239,616 ( 4 % ) ;
; Total RAM block bits                        ; 13,824 / 239,616 ( 6 % ) ;
; Embedded Multiplier 9-bit elements          ; 0 / 52 ( 0 % )           ;
; PLLs                                        ; 0 / 4 ( 0 % )            ;
; Global clocks                               ; 1 / 16 ( 6 % )           ;
; Average interconnect usage                  ; 0%                       ;
; Peak interconnect usage                     ; 1%                       ;
; Maximum fan-out node                        ; clk~clkctrl              ;
; Maximum fan-out                             ; 35                       ;
; Highest non-global fan-out signal           ; acc[22]                  ;
; Highest non-global fan-out                  ; 4                        ;
; Total fan-out                               ; 203                      ;
; Average fan-out                             ; 1.78                     ;
+---------------------------------------------+--------------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LogicLock Region Resource Usage                                                                                                                                                                                                              ;
+------------------+--------+-------+--------+-------------+---------------------------+---------------+-------------+-------+--------------+---------+-----------+-------+--------------+--------------+-------------------+------------------+
; LogicLock Region ; Origin ; Width ; Height ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks  ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins  ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ;
+------------------+--------+-------+--------+-------------+---------------------------+---------------+-------------+-------+--------------+---------+-----------+-------+--------------+--------------+-------------------+------------------+
; Root Region      ; X0_Y0  ; 51    ; 28     ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0 (0)       ; 0 (0) ; 0 (0)        ; 0 (0)   ; 0 (0)     ; 0 (0) ; 0 (0)        ; 0 (0)        ; 0 (0)             ; 0 (0)            ;
+------------------+--------+-------+--------+-------------+---------------------------+---------------+-------------+-------+--------------+---------+-----------+-------+--------------+--------------+-------------------+------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+