par_serial.vhd

来自「并入串出移位寄存器和8路并行输出串行移位寄存器的VHDL代码」· VHDL 代码 · 共 28 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;

ENTITY par_serial IS
 PORT
 (    
    clk       :     in  std_logic;
    data_in   : in  STD_LOGIC_VECTOR(7 DOWNTO 0);
    dout   : out STD_LOGIC
  
 );
END par_serial;


ARCHITECTURE Beha_bin_chuan8_01 OF par_serial IS
    SIGNAL i : integer  range 0 to 7;
begin
    process (clk)
    begin
        if clk'event and clk='1' then   
           dout<=data_in(i);
           i<=i+1;
        end if;
    end process;
end Beha_bin_chuan8_01;