serial_par.vhd

来自「并入串出移位寄存器和8路并行输出串行移位寄存器的VHDL代码」· VHDL 代码 · 共 44 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY serial_par IS
PORT
 (
  LATCH:IN STD_LOGIC;
  OE  :IN STD_LOGIC;
  CLK  :IN STD_LOGIC;
  SIN  :IN STD_LOGIC;
  DOUT :OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
  SOUT :OUT STD_LOGIC
 );
END serial_par;

ARCHITECTURE BEHAVE OF serial_par IS
 SIGNAL TEMP:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
 PROCESS(CLK)
--  VARIABLE COUNTER:INTEGER RANGE 0 TO 7;
 BEGIN
--  COUNTER:=0;
  IF(RISING_EDGE(CLK)) THEN
   TEMP(0)<=SIN;
   FOR COUNTER IN 0 TO 6 LOOP
    TEMP(COUNTER+1)<=TEMP(COUNTER);
   END LOOP;
  END IF;
 END PROCESS;
 
 PROCESS(LATCH,OE)
 BEGIN
  IF OE='1' THEN
   DOUT<="11111111";    --或者DOUT<=(others=>'1');
  ELSE IF(RISING_EDGE(LATCH)) THEN
   DOUT<=TEMP;
   SOUT<=TEMP(7);
   END IF;
  END IF;
 END PROCESS;
END BEHAVE;