prev_cmp_ram.qmsg

来自「实现简单CPU功能的源码」· QMSG 代码 · 共 51 行 · 第 1/4 页

{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component " "Info: Instantiated megafunction \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_address_control REGISTERED " "Info: Parameter \"lpm_address_control\" = \"REGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_file RAM.mif " "Info: Parameter \"lpm_file\" = \"RAM.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_indata UNREGISTERED " "Info: Parameter \"lpm_indata\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_outdata UNREGISTERED " "Info: Parameter \"lpm_outdata\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_RAM_DQ " "Info: Parameter \"lpm_type\" = \"LPM_RAM_DQ\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 16 " "Info: Parameter \"lpm_width\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthad 8 " "Info: Parameter \"lpm_widthad\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "lpm_ram_dq0.vhd" "" { Text "D:/RAM/lpm_ram_dq0.vhd" 82 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "58 " "Info: Implemented 58 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "26 " "Info: Implemented 26 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_RAMS" "16 " "Info: Implemented 16 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "149 " "Info: Allocated 149 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 21 11:08:22 2008 " "Info: Processing ended: Mon Apr 21 11:08:22 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 21 11:08:25 2008 " "Info: Processing started: Mon Apr 21 11:08:25 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM -c RAM " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM -c RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "RAM EPF10K10LC84-3 " "Info: Automatically selected device EPF10K10LC84-3 for design RAM" {  } {  } 0 0 "Automatically selected device %2!s! for design %1!s!" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "" 0}
{ "Info" "IF10KE_F10KE_WIRE_LUT_INSERTED" "0 " "Info: Inserted 0 logic cells in first fitting attempt" {  } {  } 0 0 "Inserted %1!d! logic cells in first fitting attempt" 0 0 "" 0}
{ "Info" "IFIT_FIT_ATTEMPT" "1 Mon Apr 21 2008 11:08:27 " "Info: Started fitting attempt 1 on Mon Apr 21 2008 at 11:08:27" {  } {  } 0 0 "Started fitting attempt %1!d! on %2!s! at %3!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}