prev_cmp_ram.qmsg

来自「实现简单CPU功能的源码」· QMSG 代码 · 共 51 行 · 第 1/4 页

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[15\]~mem_cell_din1 " "Warning: Node \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[15\]~mem_cell_din1\" is a latch" {  } { { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[14\]~mem_cell_din1 " "Warning: Node \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[14\]~mem_cell_din1\" is a latch" {  } { { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[13\]~mem_cell_din1 " "Warning: Node \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[13\]~mem_cell_din1\" is a latch" {  } { { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[12\]~mem_cell_din1 " "Warning: Node \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[12\]~mem_cell_din1\" is a latch" {  } { { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[11\]~mem_cell_din1 " "Warning: Node \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[11\]~mem_cell_din1\" is a latch" {  } { { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[10\]~mem_cell_din1 " "Warning: Node \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[10\]~mem_cell_din1\" is a latch" {  } { { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[9\]~mem_cell_din1 " "Warning: Node \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[9\]~mem_cell_din1\" is a latch" {  } { { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[8\]~mem_cell_din1 " "Warning: Node \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[8\]~mem_cell_din1\" is a latch" {  } { { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[7\]~mem_cell_din1 " "Warning: Node \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[7\]~mem_cell_din1\" is a latch" {  } { { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[6\]~mem_cell_din1 " "Warning: Node \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[6\]~mem_cell_din1\" is a latch" {  } { { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[5\]~mem_cell_din1 " "Warning: Node \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[5\]~mem_cell_din1\" is a latch" {  } { { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[4\]~mem_cell_din1 " "Warning: Node \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[4\]~mem_cell_din1\" is a latch" {  } { { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[3\]~mem_cell_din1 " "Warning: Node \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[3\]~mem_cell_din1\" is a latch" {  } { { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[2\]~mem_cell_din1 " "Warning: Node \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[2\]~mem_cell_din1\" is a latch" {  } { { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[1\]~mem_cell_din1 " "Warning: Node \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[1\]~mem_cell_din1\" is a latch" {  } { { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[0\]~mem_cell_din1 " "Warning: Node \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[0\]~mem_cell_din1\" is a latch" {  } { { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "inclock " "Info: Assuming node \"inclock\" is an undefined clock" {  } { { "RAM.bdf" "" { Schematic "D:/RAM/RAM.bdf" { { 168 144 312 184 "inclock" "" } } } } { "f:/program files/quartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/program files/quartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "inclock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "inclock " "Info: No valid register-to-register data paths exist for clock \"inclock\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[15\]~reg_we0 we inclock 6.200 ns memory " "Info: tsu for memory \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[15\]~reg_we0\" (data pin = \"we\", clock pin = \"inclock\") is 6.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.600 ns + Longest pin memory " "Info: + Longest pin to memory delay is 8.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns we 1 PIN PIN_84 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_84; Fanout = 16; PIN Node = 'we'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { we } "NODE_NAME" } } { "RAM.bdf" "" { Schematic "D:/RAM/RAM.bdf" { { 120 216 384 136 "we" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(5.000 ns) 8.600 ns lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[15\]~reg_we0 2 MEM EC4_B 1 " "Info: 2: + IC(1.700 ns) + CELL(5.000 ns) = 8.600 ns; Loc. = EC4_B; Fanout = 1; MEM Node = 'lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[15\]~reg_we0'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "6.700 ns" { we lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[15]~reg_we0 } "NODE_NAME" } } { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.900 ns ( 80.23 % ) " "Info: Total cell delay = 6.900 ns ( 80.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns ( 19.77 % ) " "Info: Total interconnect delay = 1.700 ns ( 19.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "8.600 ns" { we lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[15]~reg_we0 } "NODE_NAME" } } { "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "8.600 ns" { we we~out lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[15]~reg_we0 } { 0.000ns 0.000ns 1.700ns } { 0.000ns 1.900ns 5.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.500 ns + " "Info: + Micro setup delay of destination is 1.500 ns" {  } { { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclock destination 3.900 ns - Shortest memory " "Info: - Shortest clock path from clock \"inclock\" to destination memory is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns inclock 1 CLK PIN_43 288 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 288; CLK Node = 'inclock'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclock } "NODE_NAME" } } { "RAM.bdf" "" { Schematic "D:/RAM/RAM.bdf" { { 168 144 312 184 "inclock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[15\]~reg_we0 2 MEM EC4_B 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = EC4_B; Fanout = 1; MEM Node = 'lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[15\]~reg_we0'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { inclock lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[15]~reg_we0 } "NODE_NAME" } } { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { inclock lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[15]~reg_we0 } "NODE_NAME" } } { "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { inclock inclock~out lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[15]~reg_we0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "8.600 ns" { we lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[15]~reg_we0 } "NODE_NAME" } } { "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "8.600 ns" { we we~out lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[15]~reg_we0 } { 0.000ns 0.000ns 1.700ns } { 0.000ns 1.900ns 5.000ns } "" } } { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { inclock lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[15]~reg_we0 } "NODE_NAME" } } { "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { inclock inclock~out lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[15]~reg_we0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "inclock q\[5\] lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[5\]~reg_ra0 24.200 ns memory " "Info: tco from clock \"inclock\" to destination pin \"q\[5\]\" through memory \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[5\]~reg_ra0\" is 24.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclock source 3.900 ns + Longest memory " "Info: + Longest clock path from clock \"inclock\" to source memory is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns inclock 1 CLK PIN_43 288 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 288; CLK Node = 'inclock'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclock } "NODE_NAME" } } { "RAM.bdf" "" { Schematic "D:/RAM/RAM.bdf" { { 168 144 312 184 "inclock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[5\]~reg_ra0 2 MEM EC5_B 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = EC5_B; Fanout = 1; MEM Node = 'lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[5\]~reg_ra0'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { inclock lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5]~reg_ra0 } "NODE_NAME" } } { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { inclock lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5]~reg_ra0 } "NODE_NAME" } } { "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { inclock inclock~out lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5]~reg_ra0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "19.800 ns + Longest memory pin " "Info: + Longest memory to pin delay is 19.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[5\]~reg_ra0 1 MEM EC5_B 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = EC5_B; Fanout = 1; MEM Node = 'lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[5\]~reg_ra0'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5]~reg_ra0 } "NODE_NAME" } } { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.700 ns) 8.700 ns lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[5\]~mem_cell_ra0 2 MEM EC5_B 1 " "Info: 2: + IC(0.000 ns) + CELL(8.700 ns) = 8.700 ns; Loc. = EC5_B; Fanout = 1; MEM Node = 'lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[5\]~mem_cell_ra0'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "8.700 ns" { lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5]~reg_ra0 lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5]~mem_cell_ra0 } "NODE_NAME" } } { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 10.700 ns lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[5\] 3 MEM EC5_B 1 " "Info: 3: + IC(0.000 ns) + CELL(2.000 ns) = 10.700 ns; Loc. = EC5_B; Fanout = 1; MEM Node = 'lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[5\]'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5]~mem_cell_ra0 lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5] } "NODE_NAME" } } { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.200 ns) + CELL(3.900 ns) 19.800 ns q\[5\] 4 PIN PIN_24 0 " "Info: 4: + IC(5.200 ns) + CELL(3.900 ns) = 19.800 ns; Loc. = PIN_24; Fanout = 0; PIN Node = 'q\[5\]'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "9.100 ns" { lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5] q[5] } "NODE_NAME" } } { "RAM.bdf" "" { Schematic "D:/RAM/RAM.bdf" { { 96 640 816 112 "q\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.600 ns ( 73.74 % ) " "Info: Total cell delay = 14.600 ns ( 73.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.200 ns ( 26.26 % ) " "Info: Total interconnect delay = 5.200 ns ( 26.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "19.800 ns" { lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5]~reg_ra0 lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5]~mem_cell_ra0 lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5] q[5] } "NODE_NAME" } } { "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "19.800 ns" { lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5]~reg_ra0 lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5]~mem_cell_ra0 lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5] q[5] } { 0.000ns 0.000ns 0.000ns 5.200ns } { 0.000ns 8.700ns 2.000ns 3.900ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { inclock lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5]~reg_ra0 } "NODE_NAME" } } { "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { inclock inclock~out lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5]~reg_ra0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } } { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "19.800 ns" { lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5]~reg_ra0 lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5]~mem_cell_ra0 lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5] q[5] } "NODE_NAME" } } { "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "19.800 ns" { lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5]~reg_ra0 lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5]~mem_cell_ra0 lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5] q[5] } { 0.000ns 0.000ns 0.000ns 5.200ns } { 0.000ns 8.700ns 2.000ns 3.900ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "data\[5\] q\[5\] 25.500 ns Longest " "Info: Longest tpd from source pin \"data\[5\]\" to destination pin \"q\[5\]\" is 25.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns data\[5\] 1 PIN PIN_39 2 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_39; Fanout = 2; PIN Node = 'data\[5\]'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[5] } "NODE_NAME" } } { "RAM.bdf" "" { Schematic "D:/RAM/RAM.bdf" { { 96 200 368 112 "data\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(8.000 ns) 14.400 ns lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[5\]~mem_cell_din0 2 MEM EC5_B 1 " "Info: 2: + IC(3.300 ns) + CELL(8.000 ns) = 14.400 ns; Loc. = EC5_B; Fanout = 1; MEM Node = 'lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[5\]~mem_cell_din0'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "11.300 ns" { data[5] lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5]~mem_cell_din0 } "NODE_NAME" } } { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 16.400 ns lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[5\] 3 MEM EC5_B 1 " "Info: 3: + IC(0.000 ns) + CELL(2.000 ns) = 16.400 ns; Loc. = EC5_B; Fanout = 1; MEM Node = 'lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[5\]'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5]~mem_cell_din0 lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5] } "NODE_NAME" } } { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.200 ns) + CELL(3.900 ns) 25.500 ns q\[5\] 4 PIN PIN_24 0 " "Info: 4: + IC(5.200 ns) + CELL(3.900 ns) = 25.500 ns; Loc. = PIN_24; Fanout = 0; PIN Node = 'q\[5\]'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "9.100 ns" { lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5] q[5] } "NODE_NAME" } } { "RAM.bdf" "" { Schematic "D:/RAM/RAM.bdf" { { 96 640 816 112 "q\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "17.000 ns ( 66.67 % ) " "Info: Total cell delay = 17.000 ns ( 66.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.500 ns ( 33.33 % ) " "Info: Total interconnect delay = 8.500 ns ( 33.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "25.500 ns" { data[5] lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5]~mem_cell_din0 lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5] q[5] } "NODE_NAME" } } { "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "25.500 ns" { data[5] data[5]~out lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5]~mem_cell_din0 lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5] q[5] } { 0.000ns 0.000ns 3.300ns 0.000ns 5.200ns } { 0.000ns 3.100ns 8.000ns 2.000ns 3.900ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[15\]~reg_ra3 address\[3\] inclock 2.300 ns memory " "Info: th for memory \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[15\]~reg_ra3\" (data pin = \"address\[3\]\", clock pin = \"inclock\") is 2.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclock destination 3.900 ns + Longest memory " "Info: + Longest clock path from clock \"inclock\" to destination memory is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns inclock 1 CLK PIN_43 288 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 288; CLK Node = 'inclock'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclock } "NODE_NAME" } } { "RAM.bdf" "" { Schematic "D:/RAM/RAM.bdf" { { 168 144 312 184 "inclock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[15\]~reg_ra3 2 MEM EC4_B 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = EC4_B; Fanout = 1; MEM Node = 'lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[15\]~reg_ra3'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { inclock lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[15]~reg_ra3 } "NODE_NAME" } } { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { inclock lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[15]~reg_ra3 } "NODE_NAME" } } { "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { inclock inclock~out lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[15]~reg_ra3 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "2.000 ns + " "Info: + Micro hold delay of destination is 2.000 ns" {  } { { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns address\[3\] 1 PIN PIN_1 32 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_1; Fanout = 32; PIN Node = 'address\[3\]'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { address[3] } "NODE_NAME" } } { "RAM.bdf" "" { Schematic "D:/RAM/RAM.bdf" { { 136 216 384 152 "address\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(0.000 ns) 3.600 ns lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[15\]~reg_ra3 2 MEM EC4_B 1 " "Info: 2: + IC(1.700 ns) + CELL(0.000 ns) = 3.600 ns; Loc. = EC4_B; Fanout = 1; MEM Node = 'lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\|q\[15\]~reg_ra3'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { address[3] lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[15]~reg_ra3 } "NODE_NAME" } } { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 98 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 52.78 % ) " "Info: Total cell delay = 1.900 ns ( 52.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns ( 47.22 % ) " "Info: Total interconnect delay = 1.700 ns ( 47.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { address[3] lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[15]~reg_ra3 } "NODE_NAME" } } { "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { address[3] address[3]~out lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[15]~reg_ra3 } { 0.000ns 0.000ns 1.700ns } { 0.000ns 1.900ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { inclock lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[15]~reg_ra3 } "NODE_NAME" } } { "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { inclock inclock~out lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[15]~reg_ra3 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } } { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { address[3] lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[15]~reg_ra3 } "NODE_NAME" } } { "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { address[3] address[3]~out lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[15]~reg_ra3 } { 0.000ns 0.000ns 1.700ns } { 0.000ns 1.900ns 0.000ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 18 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "106 " "Info: Allocated 106 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 21 11:08:38 2008 " "Info: Processing ended: Mon Apr 21 11:08:38 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 19 s " "Info: Quartus II Full Compilation was successful. 0 errors, 19 warnings" {  } {  } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}