prev_cmp_ram.qmsg

来自「实现简单CPU功能的源码」· QMSG 代码 · 共 51 行 · 第 1/4 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 21 11:08:19 2008 " "Info: Processing started: Mon Apr 21 11:08:19 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM -c RAM " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM -c RAM" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RAM.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file RAM.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 RAM " "Info: Found entity 1: RAM" {  } { { "RAM.bdf" "" { Schematic "D:/RAM/RAM.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "RAM " "Info: Elaborating entity \"RAM\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_ram_dq0.vhd 2 1 " "Warning: Using design file lpm_ram_dq0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_ram_dq0-SYN " "Info: Found design unit 1: lpm_ram_dq0-SYN" {  } { { "lpm_ram_dq0.vhd" "" { Text "D:/RAM/lpm_ram_dq0.vhd" 54 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_ram_dq0 " "Info: Found entity 1: lpm_ram_dq0" {  } { { "lpm_ram_dq0.vhd" "" { Text "D:/RAM/lpm_ram_dq0.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_ram_dq0 lpm_ram_dq0:inst " "Info: Elaborating entity \"lpm_ram_dq0\" for hierarchy \"lpm_ram_dq0:inst\"" {  } { { "RAM.bdf" "inst" { Schematic "D:/RAM/RAM.bdf" { { 72 432 592 192 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/program files/quartus2/quartus/libraries/megafunctions/lpm_ram_dq.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/program files/quartus2/quartus/libraries/megafunctions/lpm_ram_dq.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_ram_dq " "Info: Found entity 1: lpm_ram_dq" {  } { { "lpm_ram_dq.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/lpm_ram_dq.tdf" 60 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_ram_dq lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component " "Info: Elaborating entity \"lpm_ram_dq\" for hierarchy \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\"" {  } { { "lpm_ram_dq0.vhd" "lpm_ram_dq_component" { Text "D:/RAM/lpm_ram_dq0.vhd" 82 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component " "Info: Elaborated megafunction instantiation \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\"" {  } { { "lpm_ram_dq0.vhd" "" { Text "D:/RAM/lpm_ram_dq0.vhd" 82 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altram " "Info: Found entity 1: altram" {  } { { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 90 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altram lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram " "Info: Elaborating entity \"altram\" for hierarchy \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\"" {  } { { "lpm_ram_dq.tdf" "sram" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/lpm_ram_dq.tdf" 115 6 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component " "Info: Elaborated megafunction instantiation \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\", which is child of megafunction instantiation \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\"" {  } { { "lpm_ram_dq.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/lpm_ram_dq.tdf" 115 6 0 } } { "lpm_ram_dq0.vhd" "" { Text "D:/RAM/lpm_ram_dq0.vhd" 82 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}