pc.rpt
来自「实现简单CPU功能的源码」· RPT 代码 · 共 713 行 · 第 1/3 页
RPT
713 行
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
1 - - - -- INPUT G 0 0 0 0 clk
42 - - - -- INPUT 0 0 0 16 cs18
2 - - - -- INPUT 0 0 0 8 cs19
44 - - - -- INPUT 0 0 0 16 cs20
84 - - - -- INPUT 0 0 0 2 mbr_in0
43 - - - -- INPUT 0 0 0 2 mbr_in1
18 - - A -- INPUT 0 0 0 2 mbr_in2
17 - - A -- INPUT 0 0 0 2 mbr_in3
19 - - A -- INPUT 0 0 0 2 mbr_in4
54 - - - 21 INPUT 0 0 0 2 mbr_in5
16 - - A -- INPUT 0 0 0 2 mbr_in6
48 - - - 15 INPUT 0 0 0 2 mbr_in7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: q:\information\cpu2\pc.rpt
pc
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
83 - - - 13 OUTPUT 0 1 0 0 pc_out0
70 - - A -- OUTPUT 0 1 0 0 pc_out1
69 - - A -- OUTPUT 0 1 0 0 pc_out2
52 - - - 19 OUTPUT 0 1 0 0 pc_out3
73 - - A -- OUTPUT 0 1 0 0 pc_out4
71 - - A -- OUTPUT 0 1 0 0 pc_out5
72 - - A -- OUTPUT 0 1 0 0 pc_out6
47 - - - 14 OUTPUT 0 1 0 0 pc_out7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: q:\information\cpu2\pc.rpt
pc
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - A 20 AND2 0 3 0 4 |LPM_ADD_SUB:299|addcore:adder|:125
- 6 - A 17 AND2 0 2 0 1 |LPM_ADD_SUB:299|addcore:adder|:129
- 5 - A 17 AND2 0 4 0 2 |LPM_ADD_SUB:299|addcore:adder|:137
- 1 - A 13 DFFE + 3 1 1 0 :42
- 3 - A 13 DFFE + 3 1 1 0 :44
- 4 - A 17 DFFE + 3 1 1 0 :46
- 1 - A 17 DFFE + 3 1 1 0 :48
- 8 - A 19 DFFE + 3 1 1 0 :50
- 8 - A 20 DFFE + 3 1 1 0 :52
- 5 - A 20 DFFE + 3 1 1 0 :54
- 4 - A 13 DFFE + 3 1 1 0 :56
- 8 - A 13 DFFE + 3 1 0 1 temp7 (:58)
- 6 - A 13 DFFE + 3 1 0 2 temp6 (:59)
- 8 - A 17 DFFE + 3 1 0 2 temp5 (:60)
- 3 - A 17 DFFE + 3 1 0 3 temp4 (:61)
- 2 - A 19 DFFE + 3 1 0 4 temp3 (:62)
- 7 - A 20 DFFE + 3 1 0 2 temp2 (:63)
- 2 - A 20 DFFE + 3 1 0 3 temp1 (:64)
- 2 - A 13 DFFE + 3 1 0 4 temp0 (:65)
- 7 - A 13 OR2 1 3 0 2 :309
- 5 - A 13 OR2 1 2 0 2 :327
- 7 - A 17 OR2 1 3 0 2 :339
- 2 - A 17 OR2 1 3 0 2 :351
- 1 - A 19 OR2 1 2 0 2 :363
- 6 - A 20 OR2 1 3 0 2 :375
- 1 - A 20 OR2 1 2 0 2 :387
- 4 - A 20 OR2 1 1 0 2 :399
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: q:\information\cpu2\pc.rpt
pc
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/ 96( 5%) 0/ 48( 0%) 11/ 48( 22%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: q:\information\cpu2\pc.rpt
pc
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 clk
Device-Specific Information: q:\information\cpu2\pc.rpt
pc
** EQUATIONS **
clk : INPUT;
cs18 : INPUT;
cs19 : INPUT;
cs20 : INPUT;
mbr_in0 : INPUT;
mbr_in1 : INPUT;
mbr_in2 : INPUT;
mbr_in3 : INPUT;
mbr_in4 : INPUT;
mbr_in5 : INPUT;
mbr_in6 : INPUT;
mbr_in7 : INPUT;
-- Node name is 'pc_out0'
-- Equation name is 'pc_out0', type is output
pc_out0 = _LC4_A13;
-- Node name is 'pc_out1'
-- Equation name is 'pc_out1', type is output
pc_out1 = _LC5_A20;
-- Node name is 'pc_out2'
-- Equation name is 'pc_out2', type is output
pc_out2 = _LC8_A20;
-- Node name is 'pc_out3'
-- Equation name is 'pc_out3', type is output
pc_out3 = _LC8_A19;
-- Node name is 'pc_out4'
-- Equation name is 'pc_out4', type is output
pc_out4 = _LC1_A17;
-- Node name is 'pc_out5'
-- Equation name is 'pc_out5', type is output
pc_out5 = _LC4_A17;
-- Node name is 'pc_out6'
-- Equation name is 'pc_out6', type is output
pc_out6 = _LC3_A13;
-- Node name is 'pc_out7'
-- Equation name is 'pc_out7', type is output
pc_out7 = _LC1_A13;
-- Node name is ':65' = 'temp0'
-- Equation name is 'temp0', location is LC2_A13, type is buried.
temp0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !cs18 & !cs20 & _LC4_A20
# cs18 & !cs20 & mbr_in0;
-- Node name is ':64' = 'temp1'
-- Equation name is 'temp1', location is LC2_A20, type is buried.
temp1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !cs18 & !cs20 & _LC1_A20
# cs18 & !cs20 & mbr_in1;
-- Node name is ':63' = 'temp2'
-- Equation name is 'temp2', location is LC7_A20, type is buried.
temp2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !cs18 & !cs20 & _LC6_A20
# cs18 & !cs20 & mbr_in2;
-- Node name is ':62' = 'temp3'
-- Equation name is 'temp3', location is LC2_A19, type is buried.
temp3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !cs18 & !cs20 & _LC1_A19
# cs18 & !cs20 & mbr_in3;
-- Node name is ':61' = 'temp4'
-- Equation name is 'temp4', location is LC3_A17, type is buried.
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