pc.rpt

来自「实现简单CPU功能的源码」· RPT 代码 · 共 713 行 · 第 1/3 页

temp4    = DFFE( _EQ005, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ005 = !cs18 & !cs20 &  _LC2_A17
         #  cs18 & !cs20 &  mbr_in4;

-- Node name is ':60' = 'temp5' 
-- Equation name is 'temp5', location is LC8_A17, type is buried.
temp5    = DFFE( _EQ006, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ006 = !cs18 & !cs20 &  _LC7_A17
         #  cs18 & !cs20 &  mbr_in5;

-- Node name is ':59' = 'temp6' 
-- Equation name is 'temp6', location is LC6_A13, type is buried.
temp6    = DFFE( _EQ007, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ007 = !cs18 & !cs20 &  _LC5_A13
         #  cs18 & !cs20 &  mbr_in6;

-- Node name is ':58' = 'temp7' 
-- Equation name is 'temp7', location is LC8_A13, type is buried.
temp7    = DFFE( _EQ008, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ008 = !cs18 & !cs20 &  _LC7_A13
         #  cs18 & !cs20 &  mbr_in7;

-- Node name is '|LPM_ADD_SUB:299|addcore:adder|:125' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A20', type is buried 
_LC3_A20 = LCELL( _EQ009);
  _EQ009 =  temp0 &  temp1 &  temp2;

-- Node name is '|LPM_ADD_SUB:299|addcore:adder|:129' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A17', type is buried 
_LC6_A17 = LCELL( _EQ010);
  _EQ010 =  _LC3_A20 &  temp3;

-- Node name is '|LPM_ADD_SUB:299|addcore:adder|:137' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A17', type is buried 
_LC5_A17 = LCELL( _EQ011);
  _EQ011 =  _LC3_A20 &  temp3 &  temp4 &  temp5;

-- Node name is ':42' 
-- Equation name is '_LC1_A13', type is buried 
_LC1_A13 = DFFE( _EQ012, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ012 = !cs18 & !cs20 &  _LC7_A13
         #  cs18 & !cs20 &  mbr_in7;

-- Node name is ':44' 
-- Equation name is '_LC3_A13', type is buried 
_LC3_A13 = DFFE( _EQ013, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ013 = !cs18 & !cs20 &  _LC5_A13
         #  cs18 & !cs20 &  mbr_in6;

-- Node name is ':46' 
-- Equation name is '_LC4_A17', type is buried 
_LC4_A17 = DFFE( _EQ014, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ014 = !cs18 & !cs20 &  _LC7_A17
         #  cs18 & !cs20 &  mbr_in5;

-- Node name is ':48' 
-- Equation name is '_LC1_A17', type is buried 
_LC1_A17 = DFFE( _EQ015, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ015 = !cs18 & !cs20 &  _LC2_A17
         #  cs18 & !cs20 &  mbr_in4;

-- Node name is ':50' 
-- Equation name is '_LC8_A19', type is buried 
_LC8_A19 = DFFE( _EQ016, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ016 = !cs18 & !cs20 &  _LC1_A19
         #  cs18 & !cs20 &  mbr_in3;

-- Node name is ':52' 
-- Equation name is '_LC8_A20', type is buried 
_LC8_A20 = DFFE( _EQ017, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ017 = !cs18 & !cs20 &  _LC6_A20
         #  cs18 & !cs20 &  mbr_in2;

-- Node name is ':54' 
-- Equation name is '_LC5_A20', type is buried 
_LC5_A20 = DFFE( _EQ018, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ018 = !cs18 & !cs20 &  _LC1_A20
         #  cs18 & !cs20 &  mbr_in1;

-- Node name is ':56' 
-- Equation name is '_LC4_A13', type is buried 
_LC4_A13 = DFFE( _EQ019, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ019 = !cs18 & !cs20 &  _LC4_A20
         #  cs18 & !cs20 &  mbr_in0;

-- Node name is ':309' 
-- Equation name is '_LC7_A13', type is buried 
_LC7_A13 = LCELL( _EQ020);
  _EQ020 = !temp6 &  temp7
         # !_LC5_A17 &  temp7
         #  cs19 &  _LC5_A17 &  temp6 & !temp7
         # !cs19 &  temp7;

-- Node name is ':327' 
-- Equation name is '_LC5_A13', type is buried 
_LC5_A13 = LCELL( _EQ021);
  _EQ021 = !_LC5_A17 &  temp6
         #  cs19 &  _LC5_A17 & !temp6
         # !cs19 &  temp6;

-- Node name is ':339' 
-- Equation name is '_LC7_A17', type is buried 
_LC7_A17 = LCELL( _EQ022);
  _EQ022 = !_LC6_A17 &  temp5
         # !temp4 &  temp5
         #  cs19 &  _LC6_A17 &  temp4 & !temp5
         # !cs19 &  temp5;

-- Node name is ':351' 
-- Equation name is '_LC2_A17', type is buried 
_LC2_A17 = LCELL( _EQ023);
  _EQ023 = !temp3 &  temp4
         # !_LC3_A20 &  temp4
         #  cs19 &  _LC3_A20 &  temp3 & !temp4
         # !cs19 &  temp4;

-- Node name is ':363' 
-- Equation name is '_LC1_A19', type is buried 
_LC1_A19 = LCELL( _EQ024);
  _EQ024 = !_LC3_A20 &  temp3
         #  cs19 &  _LC3_A20 & !temp3
         # !cs19 &  temp3;

-- Node name is ':375' 
-- Equation name is '_LC6_A20', type is buried 
_LC6_A20 = LCELL( _EQ025);
  _EQ025 = !temp0 &  temp2
         # !temp1 &  temp2
         #  cs19 &  temp0 &  temp1 & !temp2
         # !cs19 &  temp2;

-- Node name is ':387' 
-- Equation name is '_LC1_A20', type is buried 
_LC1_A20 = LCELL( _EQ026);
  _EQ026 =  cs19 &  temp0 & !temp1
         # !temp0 &  temp1
         # !cs19 &  temp1;

-- Node name is ':399' 
-- Equation name is '_LC4_A20', type is buried 
_LC4_A20 = LCELL( _EQ027);
  _EQ027 = !cs19 &  temp0
         #  cs19 & !temp0;



Project Information                                 q:\information\cpu2\pc.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 15,835K