📄 div8.fit.rpt
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; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
+----------------------------+
; Advanced Data - General ;
+--------------------+-------+
; Name ; Value ;
+--------------------+-------+
; Status Code ; 0 ;
; Desired User Slack ; 0 ;
; Fit Attempts ; 1 ;
+--------------------+-------+
+----------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation ;
+--------------------------------------------------------------------------------+-------+
; Name ; Value ;
+--------------------------------------------------------------------------------+-------+
; Auto Fit Point 1 - Fit Attempt 1 ; ff ;
; Mid Wire Use - Fit Attempt 1 ; 0 ;
; Mid Slack - Fit Attempt 1 ; -9967 ;
; Internal Atom Count - Fit Attempt 1 ; 3 ;
; LE/ALM Count - Fit Attempt 1 ; 3 ;
; LAB Count - Fit Attempt 1 ; 1 ;
; Outputs per Lab - Fit Attempt 1 ; 1.000 ;
; Inputs per LAB - Fit Attempt 1 ; 0.000 ;
; Global Inputs per LAB - Fit Attempt 1 ; 2.000 ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1 ; 0:1 ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1 ; 0:1 ;
; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:1 ;
; LAB Constraint 'un-route combination' - Fit Attempt 1 ; 0:1 ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1 ; 1:1 ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1 ; 1:1 ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1 ; 0:1 ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1 ; 0:1 ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1 ; 0:1 ;
; LAB Constraint 'global control signals' - Fit Attempt 1 ; 2:1 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 1:1 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1 ; 0:1 ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1 ; 1:1 ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1 ; 0:1 ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1 ; 0:1 ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:1 ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:1 ;
; LEs in Chains - Fit Attempt 1 ; 0 ;
; LEs in Long Chains - Fit Attempt 1 ; 0 ;
; LABs with Chains - Fit Attempt 1 ; 0 ;
; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;
; Time - Fit Attempt 1 ; 0 ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.006 ;
+--------------------------------------------------------------------------------+-------+
+---------------------------------------------+
; Advanced Data - Placement ;
+-------------------------------------+-------+
; Name ; Value ;
+-------------------------------------+-------+
; Early Wire Use - Fit Attempt 1 ; 0 ;
; Early Slack - Fit Attempt 1 ; -9140 ;
; Auto Fit Point 2 - Fit Attempt 1 ; ff ;
; Auto Fit Point 4 - Fit Attempt 1 ; ff ;
; Auto Fit Point 5 - Fit Attempt 1 ; ff ;
; Auto Fit Point 4 - Fit Attempt 1 ; ff ;
; Mid Wire Use - Fit Attempt 1 ; 0 ;
; Mid Slack - Fit Attempt 1 ; -7240 ;
; Auto Fit Point 5 - Fit Attempt 1 ; ff ;
; Late Wire Use - Fit Attempt 1 ; 0 ;
; Late Slack - Fit Attempt 1 ; -7240 ;
; Peak Regional Wire - Fit Attempt 1 ; 0.000 ;
; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
; Time - Fit Attempt 1 ; 0 ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.004 ;
+-------------------------------------+-------+
+---------------------------------------------+
; Advanced Data - Routing ;
+-------------------------------------+-------+
; Name ; Value ;
+-------------------------------------+-------+
; Early Wire Use - Fit Attempt 1 ; 0 ;
; Peak Regional Wire - Fit Attempt 1 ; 0 ;
; Early Slack - Fit Attempt 1 ; -6755 ;
; Mid Slack - Fit Attempt 1 ; -6755 ;
; Late Slack - Fit Attempt 1 ; -6755 ;
; Late Wire Use - Fit Attempt 1 ; 0 ;
; Time - Fit Attempt 1 ; 0 ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.013 ;
+-------------------------------------+-------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Tue May 12 10:56:29 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off div8 -c div8
Info: Selected device EPM1270T144C5 for design "div8"
Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'.
Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'.
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EPM570T144C5 is compatible
Info: Device EPM570T144I5 is compatible
Info: Device EPM1270T144I5 is compatible
Warning: No exact pin location assignment(s) for 3 pins of 3 total pins
Info: Pin clk_out not assigned to an exact location on the device
Info: Pin clk not assigned to an exact location on the device
Info: Pin clear not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 18
Info: Automatically promoted signal "clear" to use Global clock in PIN 20
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 0 bidirectional)
Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 24 pins available
Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 30 pins available
Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 30 pins available
Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 30 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to pin delay of 2.887 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X5_Y10; Fanout = 2; REG Node = 'temp[2]'
Info: 2: + IC(0.565 ns) + CELL(2.322 ns) = 2.887 ns; Loc. = PIN_139; Fanout = 0; PIN Node = 'clk_out'
Info: Total cell delay = 2.322 ns ( 80.43 % )
Info: Total interconnect delay = 0.565 ns ( 19.57 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources
Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X9_Y0 to location X17_Y11
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Optimizations that may affect the design's timing were skipped
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Generated suppressed messages file D:/实验三/div8/div8.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 4 warnings
Info: Allocated 193 megabytes of memory during processing
Info: Processing ended: Tue May 12 10:56:31 2009
Info: Elapsed time: 00:00:02
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in D:/实验三/div8/div8.fit.smsg.
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