8位加法器树乘法器的vhdl程序.txt

一种基于加法器树方法的8为乘法器的VHDL源码

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----------       8位加法器树乘法器       ----------
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY mult_8 IS
PORT (product : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
          a,b : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    reset,clk : IN STD_LOGIC
      );
END mult_8;

ARCHITECTURE bhv OF mult_8 IS
    SIGNAL d,d1,d2,d3,d4,d5,d6,d7 : STD_LOGIC_VECTOR(15 DOWNTO 0);  
    SIGNAL e,e1,e2,e3,e4,e5,e6,e7 : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
    PROCESS(a,b,clk,reset)
    BEGIN
        IF reset='1' then  --异步复位
           product<=(others=>'0');  --输出清零
        ELSIF (clk'EVENT AND clk = '1')THEN
            FOR i IN 0 TO 7 LOOP  --8b*1b
                e(i)<=a(0) AND b(i);
                e1(i)<=a(1) AND b(i);
                e2(i)<=a(2) AND b(i);
                e3(i)<=a(3) AND b(i);
                e4(i)<=a(4) AND b(i);
                e5(i)<=a(5) AND b(i);
                e6(i)<=a(6) AND b(i);
                e7(i)<=a(7) AND b(i);
           END LOOP;

               d<="00000000"&e;  --移位
               d1<="0000000"&e1&'0';
               d2<="000000"&e2&"00";
               d3<="00000"&e3&"000";
               d4<="0000"&e4&"0000";
               d5<="000"&e5&"00000";
               d6<="00"&e6&"000000";
               d7<='0'&e7&"0000000";
               product<=d+d1+d2+d3+d4+d5+d6+d7;  --相加
        END IF;
    END PROCESS;
END bhv;