ctl_lcd.fit.summary

采用FPGA控制LCD。程序中用了两个状态机

Fitter Status : Successful - Mon Aug 04 13:54:42 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : Ctl_LCD
Top-level Entity Name : Ctl_LCD
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Final
Total logic elements : 568 / 5,980 ( 9 % )
Total pins : 14 / 185 ( 8 % )
Total virtual pins : 0
Total memory bits : 512 / 92,160 ( < 1 % )
Total PLLs : 0 / 2 ( 0 % )