ctl_lcd.tan.qmsg

采用FPGA控制LCD。程序中用了两个状态机

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register LCD:inst\|Clear_cnt\[8\] register LCD:inst\|Clear_cnt\[7\] 128.17 MHz 7.802 ns Internal " "Info: Clock \"clk\" has Internal fmax of 128.17 MHz between source register \"LCD:inst\|Clear_cnt\[8\]\" and destination register \"LCD:inst\|Clear_cnt\[7\]\" (period= 7.802 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.571 ns + Longest register register " "Info: + Longest register to register delay is 7.571 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCD:inst\|Clear_cnt\[8\] 1 REG LC_X11_Y12_N0 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y12_N0; Fanout = 5; REG Node = 'LCD:inst\|Clear_cnt\[8\]'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCD:inst|Clear_cnt[8] } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.228 ns) + CELL(0.442 ns) 1.670 ns LCD:inst\|Clear_cnt\[0\]~656 2 COMB LC_X11_Y13_N1 1 " "Info: 2: + IC(1.228 ns) + CELL(0.442 ns) = 1.670 ns; Loc. = LC_X11_Y13_N1; Fanout = 1; COMB Node = 'LCD:inst\|Clear_cnt\[0\]~656'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.670 ns" { LCD:inst|Clear_cnt[8] LCD:inst|Clear_cnt[0]~656 } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.259 ns) + CELL(0.114 ns) 3.043 ns LCD:inst\|Clear_cnt\[0\]~657 3 COMB LC_X11_Y10_N0 4 " "Info: 3: + IC(1.259 ns) + CELL(0.114 ns) = 3.043 ns; Loc. = LC_X11_Y10_N0; Fanout = 4; COMB Node = 'LCD:inst\|Clear_cnt\[0\]~657'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.373 ns" { LCD:inst|Clear_cnt[0]~656 LCD:inst|Clear_cnt[0]~657 } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.219 ns) + CELL(0.114 ns) 4.376 ns LCD:inst\|Clear_cnt\[0\]~658 4 COMB LC_X12_Y12_N4 1 " "Info: 4: + IC(1.219 ns) + CELL(0.114 ns) = 4.376 ns; Loc. = LC_X12_Y12_N4; Fanout = 1; COMB Node = 'LCD:inst\|Clear_cnt\[0\]~658'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.333 ns" { LCD:inst|Clear_cnt[0]~657 LCD:inst|Clear_cnt[0]~658 } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.720 ns) + CELL(0.114 ns) 5.210 ns LCD:inst\|Clear_cnt\[0\]~659 5 COMB LC_X11_Y12_N8 16 " "Info: 5: + IC(0.720 ns) + CELL(0.114 ns) = 5.210 ns; Loc. = LC_X11_Y12_N8; Fanout = 16; COMB Node = 'LCD:inst\|Clear_cnt\[0\]~659'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.834 ns" { LCD:inst|Clear_cnt[0]~658 LCD:inst|Clear_cnt[0]~659 } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.249 ns) + CELL(1.112 ns) 7.571 ns LCD:inst\|Clear_cnt\[7\] 6 REG LC_X11_Y13_N9 4 " "Info: 6: + IC(1.249 ns) + CELL(1.112 ns) = 7.571 ns; Loc. = LC_X11_Y13_N9; Fanout = 4; REG Node = 'LCD:inst\|Clear_cnt\[7\]'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.361 ns" { LCD:inst|Clear_cnt[0]~659 LCD:inst|Clear_cnt[7] } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.896 ns ( 25.04 % ) " "Info: Total cell delay = 1.896 ns ( 25.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.675 ns ( 74.96 % ) " "Info: Total interconnect delay = 5.675 ns ( 74.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.571 ns" { LCD:inst|Clear_cnt[8] LCD:inst|Clear_cnt[0]~656 LCD:inst|Clear_cnt[0]~657 LCD:inst|Clear_cnt[0]~658 LCD:inst|Clear_cnt[0]~659 LCD:inst|Clear_cnt[7] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.571 ns" { LCD:inst|Clear_cnt[8] {} LCD:inst|Clear_cnt[0]~656 {} LCD:inst|Clear_cnt[0]~657 {} LCD:inst|Clear_cnt[0]~658 {} LCD:inst|Clear_cnt[0]~659 {} LCD:inst|Clear_cnt[7] {} } { 0.000ns 1.228ns 1.259ns 1.219ns 0.720ns 1.249ns } { 0.000ns 0.442ns 0.114ns 0.114ns 0.114ns 1.112ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.030 ns - Smallest " "Info: - Smallest clock skew is 0.030 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.405 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.405 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 7; CLK Node = 'clk'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Ctl_LCD.bdf" "" { Schematic "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/Ctl_LCD.bdf" { { 88 -184 -16 104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns fen50:inst1\|clk0 2 REG LC_X8_Y10_N7 155 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N7; Fanout = 155; REG Node = 'fen50:inst1\|clk0'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { clk fen50:inst1|clk0 } "NODE_NAME" } } { "fen50.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/fen50.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.545 ns) + CELL(0.711 ns) 7.405 ns LCD:inst\|Clear_cnt\[7\] 3 REG LC_X11_Y13_N9 4 " "Info: 3: + IC(3.545 ns) + CELL(0.711 ns) = 7.405 ns; Loc. = LC_X11_Y13_N9; Fanout = 4; REG Node = 'LCD:inst\|Clear_cnt\[7\]'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.256 ns" { fen50:inst1|clk0 LCD:inst|Clear_cnt[7] } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.07 % ) " "Info: Total cell delay = 3.115 ns ( 42.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.290 ns ( 57.93 % ) " "Info: Total interconnect delay = 4.290 ns ( 57.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.405 ns" { clk fen50:inst1|clk0 LCD:inst|Clear_cnt[7] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.405 ns" { clk {} clk~out0 {} fen50:inst1|clk0 {} LCD:inst|Clear_cnt[7] {} } { 0.000ns 0.000ns 0.745ns 3.545ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.375 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.375 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 7; CLK Node = 'clk'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Ctl_LCD.bdf" "" { Schematic "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/Ctl_LCD.bdf" { { 88 -184 -16 104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns fen50:inst1\|clk0 2 REG LC_X8_Y10_N7 155 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N7; Fanout = 155; REG Node = 'fen50:inst1\|clk0'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { clk fen50:inst1|clk0 } "NODE_NAME" } } { "fen50.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/fen50.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.515 ns) + CELL(0.711 ns) 7.375 ns LCD:inst\|Clear_cnt\[8\] 3 REG LC_X11_Y12_N0 5 " "Info: 3: + IC(3.515 ns) + CELL(0.711 ns) = 7.375 ns; Loc. = LC_X11_Y12_N0; Fanout = 5; REG Node = 'LCD:inst\|Clear_cnt\[8\]'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.226 ns" { fen50:inst1|clk0 LCD:inst|Clear_cnt[8] } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.24 % ) " "Info: Total cell delay = 3.115 ns ( 42.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.260 ns ( 57.76 % ) " "Info: Total interconnect delay = 4.260 ns ( 57.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.375 ns" { clk fen50:inst1|clk0 LCD:inst|Clear_cnt[8] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.375 ns" { clk {} clk~out0 {} fen50:inst1|clk0 {} LCD:inst|Clear_cnt[8] {} } { 0.000ns 0.000ns 0.745ns 3.515ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.405 ns" { clk fen50:inst1|clk0 LCD:inst|Clear_cnt[7] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.405 ns" { clk {} clk~out0 {} fen50:inst1|clk0 {} LCD:inst|Clear_cnt[7] {} } { 0.000ns 0.000ns 0.745ns 3.545ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.375 ns" { clk fen50:inst1|clk0 LCD:inst|Clear_cnt[8] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.375 ns" { clk {} clk~out0 {} fen50:inst1|clk0 {} LCD:inst|Clear_cnt[8] {} } { 0.000ns 0.000ns 0.745ns 3.515ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.571 ns" { LCD:inst|Clear_cnt[8] LCD:inst|Clear_cnt[0]~656 LCD:inst|Clear_cnt[0]~657 LCD:inst|Clear_cnt[0]~658 LCD:inst|Clear_cnt[0]~659 LCD:inst|Clear_cnt[7] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.571 ns" { LCD:inst|Clear_cnt[8] {} LCD:inst|Clear_cnt[0]~656 {} LCD:inst|Clear_cnt[0]~657 {} LCD:inst|Clear_cnt[0]~658 {} LCD:inst|Clear_cnt[0]~659 {} LCD:inst|Clear_cnt[7] {} } { 0.000ns 1.228ns 1.259ns 1.219ns 0.720ns 1.249ns } { 0.000ns 0.442ns 0.114ns 0.114ns 0.114ns 1.112ns } "" } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.405 ns" { clk fen50:inst1|clk0 LCD:inst|Clear_cnt[7] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.405 ns" { clk {} clk~out0 {} fen50:inst1|clk0 {} LCD:inst|Clear_cnt[7] {} } { 0.000ns 0.000ns 0.745ns 3.545ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.375 ns" { clk fen50:inst1|clk0 LCD:inst|Clear_cnt[8] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.375 ns" { clk {} clk~out0 {} fen50:inst1|clk0 {} LCD:inst|Clear_cnt[8] {} } { 0.000ns 0.000ns 0.745ns 3.515ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout\[4\] LCD:inst\|dout\[4\] 13.002 ns register " "Info: tco from clock \"clk\" to destination pin \"dout\[4\]\" through register \"LCD:inst\|dout\[4\]\" is 13.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.354 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.354 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 7; CLK Node = 'clk'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Ctl_LCD.bdf" "" { Schematic "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/Ctl_LCD.bdf" { { 88 -184 -16 104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns fen50:inst1\|clk0 2 REG LC_X8_Y10_N7 155 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N7; Fanout = 155; REG Node = 'fen50:inst1\|clk0'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { clk fen50:inst1|clk0 } "NODE_NAME" } } { "fen50.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/fen50.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.494 ns) + CELL(0.711 ns) 7.354 ns LCD:inst\|dout\[4\] 3 REG LC_X15_Y7_N1 1 " "Info: 3: + IC(3.494 ns) + CELL(0.711 ns) = 7.354 ns; Loc. = LC_X15_Y7_N1; Fanout = 1; REG Node = 'LCD:inst\|dout\[4\]'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.205 ns" { fen50:inst1|clk0 LCD:inst|dout[4] } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.36 % ) " "Info: Total cell delay = 3.115 ns ( 42.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.239 ns ( 57.64 % ) " "Info: Total interconnect delay = 4.239 ns ( 57.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.354 ns" { clk fen50:inst1|clk0 LCD:inst|dout[4] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.354 ns" { clk {} clk~out0 {} fen50:inst1|clk0 {} LCD:inst|dout[4] {} } { 0.000ns 0.000ns 0.745ns 3.494ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.424 ns + Longest register pin " "Info: + Longest register to pin delay is 5.424 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCD:inst\|dout\[4\] 1 REG LC_X15_Y7_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y7_N1; Fanout = 1; REG Node = 'LCD:inst\|dout\[4\]'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCD:inst|dout[4] } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(2.124 ns) 5.424 ns dout\[4\] 2 PIN PIN_59 0 " "Info: 2: + IC(3.300 ns) + CELL(2.124 ns) = 5.424 ns; Loc. = PIN_59; Fanout = 0; PIN Node = 'dout\[4\]'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.424 ns" { LCD:inst|dout[4] dout[4] } "NODE_NAME" } } { "Ctl_LCD.bdf" "" { Schematic "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/Ctl_LCD.bdf" { { 152 464 640 168 "dout\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 39.16 % ) " "Info: Total cell delay = 2.124 ns ( 39.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 60.84 % ) " "Info: Total interconnect delay = 3.300 ns ( 60.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.424 ns" { LCD:inst|dout[4] dout[4] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.424 ns" { LCD:inst|dout[4] {} dout[4] {} } { 0.000ns 3.300ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.354 ns" { clk fen50:inst1|clk0 LCD:inst|dout[4] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.354 ns" { clk {} clk~out0 {} fen50:inst1|clk0 {} LCD:inst|dout[4] {} } { 0.000ns 0.000ns 0.745ns 3.494ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.424 ns" { LCD:inst|dout[4] dout[4] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.424 ns" { LCD:inst|dout[4] {} dout[4] {} } { 0.000ns 3.300ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "113 " "Info: Allocated 113 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 04 13:54:50 2008 " "Info: Processing ended: Mon Aug 04 13:54:50 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}