prev_cmp_ctl_lcd.tan.qmsg

采用FPGA控制LCD。程序中用了两个状态机

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register LCD:inst\|Clear_cnt\[10\] register LCD:inst\|datetemp\[0\] 129.63 MHz 7.714 ns Internal " "Info: Clock \"clk\" has Internal fmax of 129.63 MHz between source register \"LCD:inst\|Clear_cnt\[10\]\" and destination register \"LCD:inst\|datetemp\[0\]\" (period= 7.714 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.453 ns + Longest register register " "Info: + Longest register to register delay is 7.453 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCD:inst\|Clear_cnt\[10\] 1 REG LC_X15_Y4_N2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y4_N2; Fanout = 5; REG Node = 'LCD:inst\|Clear_cnt\[10\]'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCD:inst|Clear_cnt[10] } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.258 ns) + CELL(0.590 ns) 1.848 ns LCD:inst\|Clear_cnt\[14\]~665 2 COMB LC_X15_Y5_N0 1 " "Info: 2: + IC(1.258 ns) + CELL(0.590 ns) = 1.848 ns; Loc. = LC_X15_Y5_N0; Fanout = 1; COMB Node = 'LCD:inst\|Clear_cnt\[14\]~665'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.848 ns" { LCD:inst|Clear_cnt[10] LCD:inst|Clear_cnt[14]~665 } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.228 ns) + CELL(0.114 ns) 3.190 ns LCD:inst\|Clear_cnt\[14\]~666 3 COMB LC_X14_Y7_N0 6 " "Info: 3: + IC(1.228 ns) + CELL(0.114 ns) = 3.190 ns; Loc. = LC_X14_Y7_N0; Fanout = 6; COMB Node = 'LCD:inst\|Clear_cnt\[14\]~666'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.342 ns" { LCD:inst|Clear_cnt[14]~665 LCD:inst|Clear_cnt[14]~666 } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.114 ns) 3.766 ns LCD:inst\|Selector77~774 4 COMB LC_X14_Y7_N5 3 " "Info: 4: + IC(0.462 ns) + CELL(0.114 ns) = 3.766 ns; Loc. = LC_X14_Y7_N5; Fanout = 3; COMB Node = 'LCD:inst\|Selector77~774'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.576 ns" { LCD:inst|Clear_cnt[14]~666 LCD:inst|Selector77~774 } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 339 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.114 ns) 4.310 ns LCD:inst\|Selector153~44 5 COMB LC_X14_Y7_N8 7 " "Info: 5: + IC(0.430 ns) + CELL(0.114 ns) = 4.310 ns; Loc. = LC_X14_Y7_N8; Fanout = 7; COMB Node = 'LCD:inst\|Selector153~44'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.544 ns" { LCD:inst|Selector77~774 LCD:inst|Selector153~44 } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 452 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.789 ns) + CELL(0.292 ns) 5.391 ns LCD:inst\|Selector160~25 6 COMB LC_X15_Y7_N6 1 " "Info: 6: + IC(0.789 ns) + CELL(0.292 ns) = 5.391 ns; Loc. = LC_X15_Y7_N6; Fanout = 1; COMB Node = 'LCD:inst\|Selector160~25'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.081 ns" { LCD:inst|Selector153~44 LCD:inst|Selector160~25 } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 452 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.279 ns) + CELL(0.292 ns) 6.962 ns LCD:inst\|Selector289~958 7 COMB LC_X16_Y9_N7 1 " "Info: 7: + IC(1.279 ns) + CELL(0.292 ns) = 6.962 ns; Loc. = LC_X16_Y9_N7; Fanout = 1; COMB Node = 'LCD:inst\|Selector289~958'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.571 ns" { LCD:inst|Selector160~25 LCD:inst|Selector289~958 } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.309 ns) 7.453 ns LCD:inst\|datetemp\[0\] 8 REG LC_X16_Y9_N8 10 " "Info: 8: + IC(0.182 ns) + CELL(0.309 ns) = 7.453 ns; Loc. = LC_X16_Y9_N8; Fanout = 10; REG Node = 'LCD:inst\|datetemp\[0\]'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.491 ns" { LCD:inst|Selector289~958 LCD:inst|datetemp[0] } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.825 ns ( 24.49 % ) " "Info: Total cell delay = 1.825 ns ( 24.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.628 ns ( 75.51 % ) " "Info: Total interconnect delay = 5.628 ns ( 75.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.453 ns" { LCD:inst|Clear_cnt[10] LCD:inst|Clear_cnt[14]~665 LCD:inst|Clear_cnt[14]~666 LCD:inst|Selector77~774 LCD:inst|Selector153~44 LCD:inst|Selector160~25 LCD:inst|Selector289~958 LCD:inst|datetemp[0] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.453 ns" { LCD:inst|Clear_cnt[10] {} LCD:inst|Clear_cnt[14]~665 {} LCD:inst|Clear_cnt[14]~666 {} LCD:inst|Selector77~774 {} LCD:inst|Selector153~44 {} LCD:inst|Selector160~25 {} LCD:inst|Selector289~958 {} LCD:inst|datetemp[0] {} } { 0.000ns 1.258ns 1.228ns 0.462ns 0.430ns 0.789ns 1.279ns 0.182ns } { 0.000ns 0.590ns 0.114ns 0.114ns 0.114ns 0.292ns 0.292ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.348 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 7; CLK Node = 'clk'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Ctl_LCD.bdf" "" { Schematic "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/Ctl_LCD.bdf" { { 88 -184 -16 104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns fen50:inst1\|clk0 2 REG LC_X8_Y10_N7 156 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N7; Fanout = 156; REG Node = 'fen50:inst1\|clk0'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { clk fen50:inst1|clk0 } "NODE_NAME" } } { "fen50.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/fen50.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.488 ns) + CELL(0.711 ns) 7.348 ns LCD:inst\|datetemp\[0\] 3 REG LC_X16_Y9_N8 10 " "Info: 3: + IC(3.488 ns) + CELL(0.711 ns) = 7.348 ns; Loc. = LC_X16_Y9_N8; Fanout = 10; REG Node = 'LCD:inst\|datetemp\[0\]'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.199 ns" { fen50:inst1|clk0 LCD:inst|datetemp[0] } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.39 % ) " "Info: Total cell delay = 3.115 ns ( 42.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.233 ns ( 57.61 % ) " "Info: Total interconnect delay = 4.233 ns ( 57.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.348 ns" { clk fen50:inst1|clk0 LCD:inst|datetemp[0] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.348 ns" { clk {} clk~out0 {} fen50:inst1|clk0 {} LCD:inst|datetemp[0] {} } { 0.000ns 0.000ns 0.745ns 3.488ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.348 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 7; CLK Node = 'clk'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Ctl_LCD.bdf" "" { Schematic "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/Ctl_LCD.bdf" { { 88 -184 -16 104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns fen50:inst1\|clk0 2 REG LC_X8_Y10_N7 156 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N7; Fanout = 156; REG Node = 'fen50:inst1\|clk0'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { clk fen50:inst1|clk0 } "NODE_NAME" } } { "fen50.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/fen50.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.488 ns) + CELL(0.711 ns) 7.348 ns LCD:inst\|Clear_cnt\[10\] 3 REG LC_X15_Y4_N2 5 " "Info: 3: + IC(3.488 ns) + CELL(0.711 ns) = 7.348 ns; Loc. = LC_X15_Y4_N2; Fanout = 5; REG Node = 'LCD:inst\|Clear_cnt\[10\]'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.199 ns" { fen50:inst1|clk0 LCD:inst|Clear_cnt[10] } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.39 % ) " "Info: Total cell delay = 3.115 ns ( 42.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.233 ns ( 57.61 % ) " "Info: Total interconnect delay = 4.233 ns ( 57.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.348 ns" { clk fen50:inst1|clk0 LCD:inst|Clear_cnt[10] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.348 ns" { clk {} clk~out0 {} fen50:inst1|clk0 {} LCD:inst|Clear_cnt[10] {} } { 0.000ns 0.000ns 0.745ns 3.488ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.348 ns" { clk fen50:inst1|clk0 LCD:inst|datetemp[0] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.348 ns" { clk {} clk~out0 {} fen50:inst1|clk0 {} LCD:inst|datetemp[0] {} } { 0.000ns 0.000ns 0.745ns 3.488ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.348 ns" { clk fen50:inst1|clk0 LCD:inst|Clear_cnt[10] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.348 ns" { clk {} clk~out0 {} fen50:inst1|clk0 {} LCD:inst|Clear_cnt[10] {} } { 0.000ns 0.000ns 0.745ns 3.488ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.453 ns" { LCD:inst|Clear_cnt[10] LCD:inst|Clear_cnt[14]~665 LCD:inst|Clear_cnt[14]~666 LCD:inst|Selector77~774 LCD:inst|Selector153~44 LCD:inst|Selector160~25 LCD:inst|Selector289~958 LCD:inst|datetemp[0] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.453 ns" { LCD:inst|Clear_cnt[10] {} LCD:inst|Clear_cnt[14]~665 {} LCD:inst|Clear_cnt[14]~666 {} LCD:inst|Selector77~774 {} LCD:inst|Selector153~44 {} LCD:inst|Selector160~25 {} LCD:inst|Selector289~958 {} LCD:inst|datetemp[0] {} } { 0.000ns 1.258ns 1.228ns 0.462ns 0.430ns 0.789ns 1.279ns 0.182ns } { 0.000ns 0.590ns 0.114ns 0.114ns 0.114ns 0.292ns 0.292ns 0.309ns } "" } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.348 ns" { clk fen50:inst1|clk0 LCD:inst|datetemp[0] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.348 ns" { clk {} clk~out0 {} fen50:inst1|clk0 {} LCD:inst|datetemp[0] {} } { 0.000ns 0.000ns 0.745ns 3.488ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.348 ns" { clk fen50:inst1|clk0 LCD:inst|Clear_cnt[10] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.348 ns" { clk {} clk~out0 {} fen50:inst1|clk0 {} LCD:inst|Clear_cnt[10] {} } { 0.000ns 0.000ns 0.745ns 3.488ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout\[1\] LCD:inst\|dout\[1\] 12.269 ns register " "Info: tco from clock \"clk\" to destination pin \"dout\[1\]\" through register \"LCD:inst\|dout\[1\]\" is 12.269 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.348 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 7; CLK Node = 'clk'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Ctl_LCD.bdf" "" { Schematic "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/Ctl_LCD.bdf" { { 88 -184 -16 104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns fen50:inst1\|clk0 2 REG LC_X8_Y10_N7 156 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N7; Fanout = 156; REG Node = 'fen50:inst1\|clk0'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { clk fen50:inst1|clk0 } "NODE_NAME" } } { "fen50.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/fen50.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.488 ns) + CELL(0.711 ns) 7.348 ns LCD:inst\|dout\[1\] 3 REG LC_X11_Y4_N0 1 " "Info: 3: + IC(3.488 ns) + CELL(0.711 ns) = 7.348 ns; Loc. = LC_X11_Y4_N0; Fanout = 1; REG Node = 'LCD:inst\|dout\[1\]'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.199 ns" { fen50:inst1|clk0 LCD:inst|dout[1] } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.39 % ) " "Info: Total cell delay = 3.115 ns ( 42.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.233 ns ( 57.61 % ) " "Info: Total interconnect delay = 4.233 ns ( 57.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.348 ns" { clk fen50:inst1|clk0 LCD:inst|dout[1] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.348 ns" { clk {} clk~out0 {} fen50:inst1|clk0 {} LCD:inst|dout[1] {} } { 0.000ns 0.000ns 0.745ns 3.488ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.697 ns + Longest register pin " "Info: + Longest register to pin delay is 4.697 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCD:inst\|dout\[1\] 1 REG LC_X11_Y4_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y4_N0; Fanout = 1; REG Node = 'LCD:inst\|dout\[1\]'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCD:inst|dout[1] } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.573 ns) + CELL(2.124 ns) 4.697 ns dout\[1\] 2 PIN PIN_53 0 " "Info: 2: + IC(2.573 ns) + CELL(2.124 ns) = 4.697 ns; Loc. = PIN_53; Fanout = 0; PIN Node = 'dout\[1\]'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.697 ns" { LCD:inst|dout[1] dout[1] } "NODE_NAME" } } { "Ctl_LCD.bdf" "" { Schematic "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/Ctl_LCD.bdf" { { 152 464 640 168 "dout\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 45.22 % ) " "Info: Total cell delay = 2.124 ns ( 45.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.573 ns ( 54.78 % ) " "Info: Total interconnect delay = 2.573 ns ( 54.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.697 ns" { LCD:inst|dout[1] dout[1] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.697 ns" { LCD:inst|dout[1] {} dout[1] {} } { 0.000ns 2.573ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.348 ns" { clk fen50:inst1|clk0 LCD:inst|dout[1] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.348 ns" { clk {} clk~out0 {} fen50:inst1|clk0 {} LCD:inst|dout[1] {} } { 0.000ns 0.000ns 0.745ns 3.488ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.697 ns" { LCD:inst|dout[1] dout[1] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.697 ns" { LCD:inst|dout[1] {} dout[1] {} } { 0.000ns 2.573ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "113 " "Info: Allocated 113 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 04 13:51:23 2008 " "Info: Processing ended: Mon Aug 04 13:51:23 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}