prev_cmp_ctl_lcd.tan.qmsg

采用FPGA控制LCD。程序中用了两个状态机

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 04 13:51:21 2008 " "Info: Processing started: Mon Aug 04 13:51:21 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off Ctl_LCD -c Ctl_LCD --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Ctl_LCD -c Ctl_LCD --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "Ctl_LCD.bdf" "" { Schematic "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/Ctl_LCD.bdf" { { 88 -184 -16 104 "clk" "" } } } } { "f:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "fen50:inst1\|clk0 " "Info: Detected ripple clock \"fen50:inst1\|clk0\" as buffer" {  } { { "fen50.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/fen50.v" 4 -1 0 } } { "f:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "fen50:inst1\|clk0" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}