ctl_lcd.fit.qmsg

采用FPGA控制LCD。程序中用了两个状态机

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "clk1M " "Warning: Node \"clk1M\" is assigned to location or region, but does not exist in design" {  } { { "f:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1M" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "clk50M " "Warning: Node \"clk50M\" is assigned to location or region, but does not exist in design" {  } { { "f:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk50M" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0}  } {  } 0 0 "Ignored locations or region assignments to the following nodes" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:03 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:03" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:12 " "Info: Fitter placement operations ending: elapsed time is 00:00:12" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "8.165 ns register register " "Info: Estimated most critical path is register to register delay of 8.165 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCD:inst\|Clear_cnt\[8\] 1 REG LAB_X11_Y12 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X11_Y12; Fanout = 5; REG Node = 'LCD:inst\|Clear_cnt\[8\]'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCD:inst|Clear_cnt[8] } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.969 ns) + CELL(0.442 ns) 1.411 ns LCD:inst\|Clear_cnt\[0\]~656 2 COMB LAB_X11_Y13 1 " "Info: 2: + IC(0.969 ns) + CELL(0.442 ns) = 1.411 ns; Loc. = LAB_X11_Y13; Fanout = 1; COMB Node = 'LCD:inst\|Clear_cnt\[0\]~656'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.411 ns" { LCD:inst|Clear_cnt[8] LCD:inst|Clear_cnt[0]~656 } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.251 ns) + CELL(0.114 ns) 2.776 ns LCD:inst\|Clear_cnt\[0\]~657 3 COMB LAB_X11_Y10 4 " "Info: 3: + IC(1.251 ns) + CELL(0.114 ns) = 2.776 ns; Loc. = LAB_X11_Y10; Fanout = 4; COMB Node = 'LCD:inst\|Clear_cnt\[0\]~657'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.365 ns" { LCD:inst|Clear_cnt[0]~656 LCD:inst|Clear_cnt[0]~657 } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.539 ns) + CELL(0.114 ns) 3.429 ns LCD:inst\|LessThan4~264 4 COMB LAB_X11_Y10 4 " "Info: 4: + IC(0.539 ns) + CELL(0.114 ns) = 3.429 ns; Loc. = LAB_X11_Y10; Fanout = 4; COMB Node = 'LCD:inst\|LessThan4~264'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.653 ns" { LCD:inst|Clear_cnt[0]~657 LCD:inst|LessThan4~264 } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 493 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.361 ns) + CELL(0.292 ns) 4.082 ns LCD:inst\|Selector77~776 5 COMB LAB_X11_Y10 3 " "Info: 5: + IC(0.361 ns) + CELL(0.292 ns) = 4.082 ns; Loc. = LAB_X11_Y10; Fanout = 3; COMB Node = 'LCD:inst\|Selector77~776'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.653 ns" { LCD:inst|LessThan4~264 LCD:inst|Selector77~776 } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 339 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.539 ns) + CELL(0.114 ns) 4.735 ns LCD:inst\|Selector83~814 6 COMB LAB_X11_Y10 1 " "Info: 6: + IC(0.539 ns) + CELL(0.114 ns) = 4.735 ns; Loc. = LAB_X11_Y10; Fanout = 1; COMB Node = 'LCD:inst\|Selector83~814'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.653 ns" { LCD:inst|Selector77~776 LCD:inst|Selector83~814 } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 339 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.211 ns) + CELL(0.442 ns) 5.388 ns LCD:inst\|Selector157~54 7 COMB LAB_X11_Y10 1 " "Info: 7: + IC(0.211 ns) + CELL(0.442 ns) = 5.388 ns; Loc. = LAB_X11_Y10; Fanout = 1; COMB Node = 'LCD:inst\|Selector157~54'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.653 ns" { LCD:inst|Selector83~814 LCD:inst|Selector157~54 } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 452 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.361 ns) + CELL(0.292 ns) 6.041 ns LCD:inst\|Selector157~55 8 COMB LAB_X11_Y10 1 " "Info: 8: + IC(0.361 ns) + CELL(0.292 ns) = 6.041 ns; Loc. = LAB_X11_Y10; Fanout = 1; COMB Node = 'LCD:inst\|Selector157~55'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.653 ns" { LCD:inst|Selector157~54 LCD:inst|Selector157~55 } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 452 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.539 ns) + CELL(0.114 ns) 6.694 ns LCD:inst\|Selector285~1071 9 COMB LAB_X11_Y10 1 " "Info: 9: + IC(0.539 ns) + CELL(0.114 ns) = 6.694 ns; Loc. = LAB_X11_Y10; Fanout = 1; COMB Node = 'LCD:inst\|Selector285~1071'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.653 ns" { LCD:inst|Selector157~55 LCD:inst|Selector285~1071 } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.063 ns) + CELL(0.590 ns) 7.347 ns LCD:inst\|Selector285~1072 10 COMB LAB_X11_Y10 1 " "Info: 10: + IC(0.063 ns) + CELL(0.590 ns) = 7.347 ns; Loc. = LAB_X11_Y10; Fanout = 1; COMB Node = 'LCD:inst\|Selector285~1072'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.653 ns" { LCD:inst|Selector285~1071 LCD:inst|Selector285~1072 } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.211 ns) + CELL(0.607 ns) 8.165 ns LCD:inst\|datetemp\[3\] 11 REG LAB_X11_Y10 12 " "Info: 11: + IC(0.211 ns) + CELL(0.607 ns) = 8.165 ns; Loc. = LAB_X11_Y10; Fanout = 12; REG Node = 'LCD:inst\|datetemp\[3\]'" {  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.818 ns" { LCD:inst|Selector285~1072 LCD:inst|datetemp[3] } "NODE_NAME" } } { "LCD.v" "" { Text "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/LCD.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.121 ns ( 38.22 % ) " "Info: Total cell delay = 3.121 ns ( 38.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.044 ns ( 61.78 % ) " "Info: Total interconnect delay = 5.044 ns ( 61.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.165 ns" { LCD:inst|Clear_cnt[8] LCD:inst|Clear_cnt[0]~656 LCD:inst|Clear_cnt[0]~657 LCD:inst|LessThan4~264 LCD:inst|Selector77~776 LCD:inst|Selector83~814 LCD:inst|Selector157~54 LCD:inst|Selector157~55 LCD:inst|Selector285~1071 LCD:inst|Selector285~1072 LCD:inst|datetemp[3] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 " "Info: Average interconnect usage is 2% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "5 X12_Y0 X23_Y10 " "Info: Peak interconnect usage is 5% of the available device resources in the region that extends from location X12_Y0 to location X23_Y10" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Info: Fitter routing operations ending: elapsed time is 00:00:04" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "rd VCC " "Info: Pin rd has VCC driving its datain port" {  } { { "f:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/altera/72/quartus/bin/pin_planner.ppl" { rd } } } { "f:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "rd" } } } } { "Ctl_LCD.bdf" "" { Schematic "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/Ctl_LCD.bdf" { { 368 448 624 384 "rd" "" } } } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rd } "NODE_NAME" } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rd } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/Ctl_LCD.fit.smsg " "Info: Generated suppressed messages file C:/Documents and Settings/HAILONG_SHI.005895E690D643A/桌面/0730_Ctl_LCD/Ctl_LCD.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "172 " "Info: Allocated 172 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 04 13:54:42 2008 " "Info: Processing ended: Mon Aug 04 13:54:42 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Info: Elapsed time: 00:00:28" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}