ctl_lcd.hier_info

采用FPGA控制LCD。程序中用了两个状态机

|Ctl_LCD
cs <= LCD:inst.cs
clk => fen50:inst1.clk
wr <= LCD:inst.wr
a0 <= LCD:inst.a0
rd <= <VCC>
reset <= LCD:inst.reset
dout[0] <= LCD:inst.dout[0]
dout[1] <= LCD:inst.dout[1]
dout[2] <= LCD:inst.dout[2]
dout[3] <= LCD:inst.dout[3]
dout[4] <= LCD:inst.dout[4]
dout[5] <= LCD:inst.dout[5]
dout[6] <= LCD:inst.dout[6]
dout[7] <= LCD:inst.dout[7]


|Ctl_LCD|LCD:inst
clk => sub_state[7].CLK
clk => sub_state[6].CLK
clk => sub_state[5].CLK
clk => sub_state[4].CLK
clk => sub_state[3].CLK
clk => sub_state[2].CLK
clk => sub_state[1].CLK
clk => sub_state[0].CLK
clk => wr~reg0.CLK
clk => cs~reg0.CLK
clk => reset~reg0.CLK
clk => delay_cnt[15].CLK
clk => delay_cnt[14].CLK
clk => delay_cnt[13].CLK
clk => delay_cnt[12].CLK
clk => delay_cnt[11].CLK
clk => delay_cnt[10].CLK
clk => delay_cnt[9].CLK
clk => delay_cnt[8].CLK
clk => delay_cnt[7].CLK
clk => delay_cnt[6].CLK
clk => delay_cnt[5].CLK
clk => delay_cnt[4].CLK
clk => delay_cnt[3].CLK
clk => delay_cnt[2].CLK
clk => delay_cnt[1].CLK
clk => delay_cnt[0].CLK
clk => Cursor_addr[15].CLK
clk => Cursor_addr[14].CLK
clk => Cursor_addr[13].CLK
clk => Cursor_addr[12].CLK
clk => Cursor_addr[11].CLK
clk => Cursor_addr[10].CLK
clk => Cursor_addr[9].CLK
clk => Cursor_addr[8].CLK
clk => Cursor_addr[7].CLK
clk => Cursor_addr[6].CLK
clk => Cursor_addr[5].CLK
clk => Cursor_addr[4].CLK
clk => Cursor_addr[3].CLK
clk => Cursor_addr[2].CLK
clk => Cursor_addr[1].CLK
clk => Cursor_addr[0].CLK
clk => Cursor_addr0[15].CLK
clk => Cursor_addr0[14].CLK
clk => Cursor_addr0[13].CLK
clk => Cursor_addr0[12].CLK
clk => Cursor_addr0[11].CLK
clk => Cursor_addr0[10].CLK
clk => Cursor_addr0[9].CLK
clk => Cursor_addr0[8].CLK
clk => Cursor_addr0[7].CLK
clk => Cursor_addr0[6].CLK
clk => Cursor_addr0[5].CLK
clk => Cursor_addr0[4].CLK
clk => Cursor_addr0[3].CLK
clk => Cursor_addr0[2].CLK
clk => Cursor_addr0[1].CLK
clk => Cursor_addr0[0].CLK
clk => com_flag.CLK
clk => datetemp[7].CLK
clk => datetemp[6].CLK
clk => datetemp[5].CLK
clk => datetemp[4].CLK
clk => datetemp[3].CLK
clk => datetemp[2].CLK
clk => datetemp[1].CLK
clk => datetemp[0].CLK
clk => hanzi_cnt[7].CLK
clk => hanzi_cnt[6].CLK
clk => hanzi_cnt[5].CLK
clk => hanzi_cnt[4].CLK
clk => hanzi_cnt[3].CLK
clk => hanzi_cnt[2].CLK
clk => hanzi_cnt[1].CLK
clk => hanzi_cnt[0].CLK
clk => a0~reg0.CLK
clk => dout[7]~reg0.CLK
clk => dout[6]~reg0.CLK
clk => dout[5]~reg0.CLK
clk => dout[4]~reg0.CLK
clk => dout[3]~reg0.CLK
clk => dout[2]~reg0.CLK
clk => dout[1]~reg0.CLK
clk => dout[0]~reg0.CLK
clk => Byte_cnt[7].CLK
clk => Byte_cnt[6].CLK
clk => Byte_cnt[5].CLK
clk => Byte_cnt[4].CLK
clk => Byte_cnt[3].CLK
clk => Byte_cnt[2].CLK
clk => Byte_cnt[1].CLK
clk => Byte_cnt[0].CLK
clk => addr[5]~reg0.CLK
clk => addr[4]~reg0.CLK
clk => addr[3]~reg0.CLK
clk => addr[2]~reg0.CLK
clk => addr[1]~reg0.CLK
clk => addr[0]~reg0.CLK
clk => Clear_cnt[15].CLK
clk => Clear_cnt[14].CLK
clk => Clear_cnt[13].CLK
clk => Clear_cnt[12].CLK
clk => Clear_cnt[11].CLK
clk => Clear_cnt[10].CLK
clk => Clear_cnt[9].CLK
clk => Clear_cnt[8].CLK
clk => Clear_cnt[7].CLK
clk => Clear_cnt[6].CLK
clk => Clear_cnt[5].CLK
clk => Clear_cnt[4].CLK
clk => Clear_cnt[3].CLK
clk => Clear_cnt[2].CLK
clk => Clear_cnt[1].CLK
clk => Clear_cnt[0].CLK
clk => char[7].CLK
clk => char[6].CLK
clk => char[5].CLK
clk => char[4].CLK
clk => char[3].CLK
clk => char[2].CLK
clk => char[1].CLK
clk => char[0].CLK
clk => Interupt~8.IN1
clk => breakpoint~20.IN1
clk => state~139.IN1
din[0] => datetemp~7.DATAB
din[1] => datetemp~6.DATAB
din[2] => datetemp~5.DATAB
din[3] => datetemp~4.DATAB
din[4] => datetemp~3.DATAB
din[5] => datetemp~2.DATAB
din[6] => datetemp~1.DATAB
din[7] => datetemp~0.DATAB
wr <= wr~reg0.DB_MAX_OUTPUT_PORT_TYPE
cs <= cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
a0 <= a0~reg0.DB_MAX_OUTPUT_PORT_TYPE
reset <= reset~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[0] <= dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= dout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= dout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= dout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= dout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= dout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= dout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= dout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr[0] <= addr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr[1] <= addr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr[2] <= addr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr[3] <= addr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr[4] <= addr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr[5] <= addr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|Ctl_LCD|fen50:inst1
clk => count[5].CLK
clk => count[4].CLK
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clk => clk0~reg0.CLK
clk0 <= clk0~reg0.DB_MAX_OUTPUT_PORT_TYPE


|Ctl_LCD|lpm_rom0:inst4
address[0] => address[0]~5.IN1
address[1] => address[1]~4.IN1
address[2] => address[2]~3.IN1
address[3] => address[3]~2.IN1
address[4] => address[4]~1.IN1
address[5] => address[5]~0.IN1
clock => clock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a


|Ctl_LCD|lpm_rom0:inst4|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_0431:auto_generated.address_a[0]
address_a[1] => altsyncram_0431:auto_generated.address_a[1]
address_a[2] => altsyncram_0431:auto_generated.address_a[2]
address_a[3] => altsyncram_0431:auto_generated.address_a[3]
address_a[4] => altsyncram_0431:auto_generated.address_a[4]
address_a[5] => altsyncram_0431:auto_generated.address_a[5]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_0431:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_0431:auto_generated.q_a[0]
q_a[1] <= altsyncram_0431:auto_generated.q_a[1]
q_a[2] <= altsyncram_0431:auto_generated.q_a[2]
q_a[3] <= altsyncram_0431:auto_generated.q_a[3]
q_a[4] <= altsyncram_0431:auto_generated.q_a[4]
q_a[5] <= altsyncram_0431:auto_generated.q_a[5]
q_a[6] <= altsyncram_0431:auto_generated.q_a[6]
q_a[7] <= altsyncram_0431:auto_generated.q_a[7]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|Ctl_LCD|lpm_rom0:inst4|altsyncram:altsyncram_component|altsyncram_0431:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT