fen50.v

来自「采用FPGA控制LCD。程序中用了两个状态机」· Verilog 代码 · 共 19 行

module fen50(clk,clk0);

input clk;
output clk0;

reg clk0;
reg[5:0] count;

always@(posedge clk)
	begin
		if(count>=49) count<=6'd0;
		else count<=count+1'b1;
		if(count<=24) clk0<=1'b1;
		else clk0<=1'b0;
	end
	
endmodule