ctl_lcd.qsf

采用FPGA控制LCD。程序中用了两个状态机

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		Ctl_LCD_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C6Q240C8
set_global_assignment -name TOP_LEVEL_ENTITY Ctl_LCD
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:09:35  JULY 30, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 7.2
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name BDF_FILE Ctl_LCD.bdf
set_global_assignment -name VERILOG_FILE LCD.v
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_location_assignment PIN_45 -to a0
set_location_assignment PIN_28 -to clk
set_location_assignment PIN_43 -to cs
set_location_assignment PIN_56 -to dout[7]
set_location_assignment PIN_58 -to dout[6]
set_location_assignment PIN_60 -to dout[5]
set_location_assignment PIN_59 -to dout[4]
set_location_assignment PIN_57 -to dout[3]
set_location_assignment PIN_55 -to dout[2]
set_location_assignment PIN_53 -to dout[1]
set_location_assignment PIN_49 -to dout[0]
set_location_assignment PIN_41 -to rd
set_location_assignment PIN_38 -to wr
set_global_assignment -name VECTOR_WAVEFORM_FILE Ctl_LCD.vwf
set_global_assignment -name VERILOG_FILE fen50.v
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_location_assignment PIN_54 -to clk50M
set_location_assignment PIN_50 -to clk1M
set_location_assignment PIN_47 -to reset
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
set_global_assignment -name INCREMENTAL_COMPILATION OFF
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"