sevenvote.vhd

本设计师一个7人表决器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY SEVENVOTE IS
	PORT(
            VOTE  : IN       STD_LOGIC_VECTOR(6 DOWNTO 0); 					 		
		 	VOUT1 : BUFFER   STD_LOGIC;
            VOUT2 : BUFFER   STD_LOGIC			
		);
END SEVENVOTE;

--*********************************************
ARCHITECTURE ART OF SEVENVOTE IS
  BEGIN
  PROCESS(VOTE)  
  VARIABLE VOTEOUT : STD_LOGIC_VECTOR(2 downto 0);   
  BEGIN
    VOTEOUT:="000";
    FOR i IN 0 TO 6 LOOP
      IF VOTE(i)='1' THEN
         VOTEOUT:=VOTEOUT+1;
      END IF;
    END LOOP;
    VOUT1<=VOTEOUT(2);
    VOUT2<=NOT VOUT1;  
   END PROCESS;
END ART;