project3.tan.rpt

用VHDL语言实现一个10秒倒计时电路

; N/A   ; None         ; 12.987 ns  ; col[2]~reg0 ; col[2] ; clk        ;
; N/A   ; None         ; 12.986 ns  ; col[7]~reg0 ; col[7] ; clk        ;
; N/A   ; None         ; 12.963 ns  ; col[6]~reg0 ; col[6] ; clk        ;
; N/A   ; None         ; 12.937 ns  ; col[4]~reg0 ; col[4] ; clk        ;
; N/A   ; None         ; 12.925 ns  ; col[5]~reg0 ; col[5] ; clk        ;
; N/A   ; None         ; 12.908 ns  ; row[3]~reg0 ; row[2] ; clk        ;
; N/A   ; None         ; 12.895 ns  ; row[3]~reg0 ; row[3] ; clk        ;
; N/A   ; None         ; 12.869 ns  ; row[4]~reg0 ; row[4] ; clk        ;
; N/A   ; None         ; 12.842 ns  ; row[5]~reg0 ; row[5] ; clk        ;
; N/A   ; None         ; 12.813 ns  ; col[0]~reg0 ; col[0] ; clk        ;
; N/A   ; None         ; 12.720 ns  ; row[6]~reg0 ; row[6] ; clk        ;
+-------+--------------+------------+-------------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Wed Dec 24 00:19:53 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off project3 -c project3
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "cou1" as buffer
    Info: Detected ripple clock "clk2" as buffer
    Info: Detected ripple clock "clk1" as buffer
Info: Clock "clk" has Internal fmax of 59.72 MHz between source register "ctrl_c[1]" and destination register "alarm~reg0" (period= 16.744 ns)
    Info: + Longest register to register delay is 2.485 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y7_N4; Fanout = 9; REG Node = 'ctrl_c[1]'
        Info: 2: + IC(1.078 ns) + CELL(0.511 ns) = 1.589 ns; Loc. = LC_X8_Y7_N1; Fanout = 2; COMB Node = 'Equal3~62'
        Info: 3: + IC(0.305 ns) + CELL(0.591 ns) = 2.485 ns; Loc. = LC_X8_Y7_N2; Fanout = 3; REG Node = 'alarm~reg0'
        Info: Total cell delay = 1.102 ns ( 44.35 % )
        Info: Total interconnect delay = 1.383 ns ( 55.65 % )
    Info: - Smallest clock skew is -5.178 ns
        Info: + Shortest clock path from clock "clk" to destination register is 8.715 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 39; CLK Node = 'clk'
            Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X15_Y3_N2; Fanout = 6; REG Node = 'clk2'
            Info: 3: + IC(3.602 ns) + CELL(0.918 ns) = 8.715 ns; Loc. = LC_X8_Y7_N2; Fanout = 3; REG Node = 'alarm~reg0'
            Info: Total cell delay = 3.375 ns ( 38.73 % )
            Info: Total interconnect delay = 5.340 ns ( 61.27 % )
        Info: - Longest clock path from clock "clk" to source register is 13.893 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 39; CLK Node = 'clk'
            Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N9; Fanout = 22; REG Node = 'clk1'
            Info: 3: + IC(3.023 ns) + CELL(1.294 ns) = 8.512 ns; Loc. = LC_X10_Y4_N4; Fanout = 3; REG Node = 'cou1'
            Info: 4: + IC(4.463 ns) + CELL(0.918 ns) = 13.893 ns; Loc. = LC_X8_Y7_N4; Fanout = 9; REG Node = 'ctrl_c[1]'
            Info: Total cell delay = 4.669 ns ( 33.61 % )
            Info: Total interconnect delay = 9.224 ns ( 66.39 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
Info: tco from clock "clk" to destination pin "alarm" through register "alarm~reg0" is 13.652 ns
    Info: + Longest clock path from clock "clk" to source register is 8.715 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 39; CLK Node = 'clk'
        Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X15_Y3_N2; Fanout = 6; REG Node = 'clk2'
        Info: 3: + IC(3.602 ns) + CELL(0.918 ns) = 8.715 ns; Loc. = LC_X8_Y7_N2; Fanout = 3; REG Node = 'alarm~reg0'
        Info: Total cell delay = 3.375 ns ( 38.73 % )
        Info: Total interconnect delay = 5.340 ns ( 61.27 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 4.561 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y7_N2; Fanout = 3; REG Node = 'alarm~reg0'
        Info: 2: + IC(2.239 ns) + CELL(2.322 ns) = 4.561 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'alarm'
        Info: Total cell delay = 2.322 ns ( 50.91 % )
        Info: Total interconnect delay = 2.239 ns ( 49.09 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 116 megabytes of memory during processing
    Info: Processing ended: Wed Dec 24 00:19:54 2008
    Info: Elapsed time: 00:00:01