📄 fenpin.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" { } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 5 -1 0 } } { "g:/program files/quartus/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "g:/program files/quartus/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register tmp\[2\] register clout~reg0 76.92 MHz 13.0 ns Internal " "Info: Clock clk has Internal fmax of 76.92 MHz between source register tmp\[2\] and destination register clout~reg0 (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tmp\[2\] 1 REG LC4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4; Fanout = 2; REG Node = 'tmp\[2\]'" { } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "" { tmp[2] } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns clout~reg0 2 REG LC3 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC3; Fanout = 1; REG Node = 'clout~reg0'" { } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "8.000 ns" { tmp[2] clout~reg0 } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" { } { } 0} } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "8.000 ns" { tmp[2] clout~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" { } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns clout~reg0 2 REG LC3 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 1; REG Node = 'clout~reg0'" { } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "0.000 ns" { clk clout~reg0 } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "3.000 ns" { clk clout~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" { } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns tmp\[2\] 2 REG LC4 2 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC4; Fanout = 2; REG Node = 'tmp\[2\]'" { } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "0.000 ns" { clk tmp[2] } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "3.000 ns" { clk tmp[2] } "NODE_NAME" } } } } 0} } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "3.000 ns" { clk clout~reg0 } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "3.000 ns" { clk tmp[2] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 15 -1 0 } } } 0} } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "8.000 ns" { tmp[2] clout~reg0 } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "3.000 ns" { clk clout~reg0 } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "3.000 ns" { clk tmp[2] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "clout~reg0 clr clk 11.000 ns register " "Info: tsu for register clout~reg0 (data pin = clr, clock pin = clk) is 11.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest pin register " "Info: + Longest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clr 1 PIN PIN_1 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 4; PIN Node = 'clr'" { } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "" { clr } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns clout~reg0 2 REG LC3 1 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC3; Fanout = 1; REG Node = 'clout~reg0'" { } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "7.000 ns" { clr clout~reg0 } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 90.00 % " "Info: Total cell delay = 9.000 ns ( 90.00 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.00 % " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" { } { } 0} } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "10.000 ns" { clr clout~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" { } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns clout~reg0 2 REG LC3 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 1; REG Node = 'clout~reg0'" { } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "0.000 ns" { clk clout~reg0 } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "3.000 ns" { clk clout~reg0 } "NODE_NAME" } } } } 0} } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "10.000 ns" { clr clout~reg0 } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "3.000 ns" { clk clout~reg0 } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk clout clout~reg0 8.000 ns register " "Info: tco from clock clk to destination pin clout through register clout~reg0 is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" { } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns clout~reg0 2 REG LC3 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 1; REG Node = 'clout~reg0'" { } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "0.000 ns" { clk clout~reg0 } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "3.000 ns" { clk clout~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest register pin " "Info: + Longest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clout~reg0 1 REG LC3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 1; REG Node = 'clout~reg0'" { } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "" { clout~reg0 } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns clout 2 PIN PIN_12 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'clout'" { } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "4.000 ns" { clout~reg0 clout } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 100.00 % " "Info: Total cell delay = 4.000 ns ( 100.00 % )" { } { } 0} } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "4.000 ns" { clout~reg0 clout } "NODE_NAME" } } } } 0} } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "3.000 ns" { clk clout~reg0 } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "4.000 ns" { clout~reg0 clout } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_TH_RESULT" "clout~reg0 clr clk -3.000 ns register " "Info: th for register clout~reg0 (data pin = clr, clock pin = clk) is -3.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" { } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns clout~reg0 2 REG LC3 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 1; REG Node = 'clout~reg0'" { } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "0.000 ns" { clk clout~reg0 } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "3.000 ns" { clk clout~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" { } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clr 1 PIN PIN_1 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 4; PIN Node = 'clr'" { } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "" { clr } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns clout~reg0 2 REG LC3 1 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC3; Fanout = 1; REG Node = 'clout~reg0'" { } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "7.000 ns" { clr clout~reg0 } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 90.00 % " "Info: Total cell delay = 9.000 ns ( 90.00 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.00 % " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" { } { } 0} } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "10.000 ns" { clr clout~reg0 } "NODE_NAME" } } } } 0} } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "3.000 ns" { clk clout~reg0 } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "10.000 ns" { clr clout~reg0 } "NODE_NAME" } } } } 0}
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