reg24lpm.v

verilog 范例

// MAX+plus II Verilog Example
// LPM Component Instantiation
// Copyright (c) 1997 Altera Corporation

module reg24lpm ( d, clk, q);

   input [23:0]d;
   input clk;
   output [23:0]q;

   lpm_ff reg12a (.q (q[11:0]), .data(d[11:0]), .clock(clk));
       defparam reg12a.lpm_width = 12;

   lpm_ff reg12b (.q (q[23:12]), .data(d[23:12]), .clock(clk));
       defparam reg12b.lpm_width = 12;

endmodule