reg24.v

verilog 范例

// MAX+plus II Verilog Example
// User-Defined Macrofunction
// Copyright (c) 1997 Altera Corporation

module reg24 ( d, clk, q);

   input [23:0]d;
   input clk;
   output [23:0]q;

   reg12 reg12a (.q (q[11:0]), .d(d[11:0]), .clk(clk));
   reg12 reg12b (.q (q[23:12]), .d(d[23:12]), .clk(clk));

endmodule