plj.fit.summary

基于CPLD的数字频率计

Fitter Status : Successful - Sat Jan 10 14:37:23 2009
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : plj
Top-level Entity Name : F
Family : MAX II
Device : EPM1270GT144C5
Timing Models : Final
Total logic elements : 303 / 1,270 ( 24 % )
Total pins : 20 / 116 ( 17 % )
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )