freq.vhd

基于CPLD的数字频率计

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FREQ IS
 PORT(FSIN:IN STD_LOGIC;
       CLK:IN STD_LOGIC;
       DOUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END FREQ;
ARCHITECTURE ART OF FREQ IS
COMPONENT CNT10  --待调用的有时钟使能的十进制计数器端口定义
         PORT(CLK,CLR,ENA:IN STD_LOGIC;
        CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        CARRY_OUT:OUT STD_LOGIC);
END COMPONENT;
COMPONENT REG32B  --待调用的32位锁存器端口定义
 PORT(LOAD:IN STD_LOGIC;
       DIN:IN STD_LOGIC_VECTOR(31 DOWNTO 0);
       DOUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END COMPONENT;
COMPONENT TESTCTL  --待调用的测频控制信号发生器端口定义 
 PORT (CLK:IN STD_LOGIC;    		--1 Hz测频控制时钟
          TSTEN:OUT STD_LOGIC;    	--计数器时钟使能
          CLR_CNT:OUT STD_LOGIC;    	--计数器清零
          LOAD:OUT STD_LOGIC);    	--输出锁存信号
END COMPONENT;
  SIGNAL TSTEN:STD_LOGIC;
  SIGNAL CLR_CNT:STD_LOGIC;
  SIGNAL LOAD:STD_LOGIC;
  SIGNAL CARRY1:STD_LOGIC;
  SIGNAL CARRY2:STD_LOGIC;
  SIGNAL CARRY3:STD_LOGIC;
  SIGNAL CARRY4:STD_LOGIC;
  SIGNAL CARRY5:STD_LOGIC;
  SIGNAL CARRY6:STD_LOGIC;
  SIGNAL CARRY7:STD_LOGIC;
  SIGNAL CARRY8:STD_LOGIC;
  SIGNAL DIN:STD_LOGIC_VECTOR(31 DOWNTO 0); 
BEGIN
U0:TESTCTL PORT MAP(CLK=>CLK,TSTEN=>TSTEN,
        CLR_CNT=>CLR_CNT,LOAD=>LOAD);
U1:CNT10 PORT MAP(CLK=>FSIN,CLR=>CLR_CNT,ENA=>TSTEN,
        CQ=>DIN (3 DOWNTO 0),CARRY_OUT=>CARRY1);
U2:CNT10 PORT MAP(CLK=>CARRY1,CLR=>CLR_CNT,ENA=>TSTEN,
        CQ=>DIN (7 DOWNTO 4),CARRY_OUT=>CARRY2);
U3:CNT10 PORT MAP(CLK=>CARRY2,CLR=>CLR_CNT,ENA=>TSTEN,
        CQ=>DIN (11 DOWNTO 8),CARRY_OUT=>CARRY3);
U4:CNT10 PORT MAP(CLK=>CARRY3,CLR=>CLR_CNT,ENA=>TSTEN,
        CQ=>DIN (15 DOWNTO 12),CARRY_OUT=>CARRY4); 
U5:CNT10 PORT MAP(CLK=>CARRY4,CLR=>CLR_CNT,ENA=>TSTEN,
        CQ=>DIN (19 DOWNTO 16),CARRY_OUT=>CARRY5);
U6:CNT10 PORT MAP(CLK=>CARRY5,CLR=>CLR_CNT,ENA=>TSTEN,
        CQ=>DIN (23 DOWNTO 20),CARRY_OUT=>CARRY6);
U7:CNT10 PORT MAP(CLK=>CARRY6,CLR=>CLR_CNT,ENA=>TSTEN,
        CQ=>DIN (27 DOWNTO 24),CARRY_OUT=>CARRY7);
U8:CNT10 PORT MAP(CLK=>CARRY7,CLR=>CLR_CNT,ENA=>TSTEN,
        CQ=>DIN (31 DOWNTO 28),CARRY_OUT=>CARRY8);
U9:REG32B PORT MAP(LOAD=>LOAD,DIN=>DIN(31 DOWNTO 0),DOUT=>DOUT);
END ART;