plj.map.qmsg

基于CPLD的数字频率计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jan 10 14:37:06 2009 " "Info: Processing started: Sat Jan 10 14:37:06 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off plj -c plj " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off plj -c plj" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CNT10.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file CNT10.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CNT10-ART " "Info: Found design unit 1: CNT10-ART" {  } { { "CNT10.vhd" "" { Text "F:/数字频率计1/CNT10.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 CNT10 " "Info: Found entity 1: CNT10" {  } { { "CNT10.vhd" "" { Text "F:/数字频率计1/CNT10.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "REG32B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file REG32B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 REG32B-ART " "Info: Found design unit 1: REG32B-ART" {  } { { "REG32B.vhd" "" { Text "F:/数字频率计1/REG32B.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 REG32B " "Info: Found entity 1: REG32B" {  } { { "REG32B.vhd" "" { Text "F:/数字频率计1/REG32B.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TESTCTL.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file TESTCTL.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 TESTCTL-ART " "Info: Found design unit 1: TESTCTL-ART" {  } { { "TESTCTL.vhd" "" { Text "F:/数字频率计1/TESTCTL.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 TESTCTL " "Info: Found entity 1: TESTCTL" {  } { { "TESTCTL.vhd" "" { Text "F:/数字频率计1/TESTCTL.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FREQ.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file FREQ.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FREQ-ART " "Info: Found design unit 1: FREQ-ART" {  } { { "FREQ.vhd" "" { Text "F:/数字频率计1/FREQ.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 FREQ " "Info: Found entity 1: FREQ" {  } { { "FREQ.vhd" "" { Text "F:/数字频率计1/FREQ.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "F.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file F.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 F " "Info: Found entity 1: F" {  } { { "F.bdf" "" { Schematic "F:/数字频率计1/F.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "kz.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file kz.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 kz-behave " "Info: Found design unit 1: kz-behave" {  } { { "kz.vhd" "" { Text "F:/数字频率计1/kz.vhd" 20 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 KZ " "Info: Found entity 1: KZ" {  } { { "kz.vhd" "" { Text "F:/数字频率计1/kz.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/数字频率计1/xinashi.vhd " "Warning: Can't analyze file -- file F:/数字频率计1/xinashi.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "xiANshi.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file xiANshi.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 XIANSHI-behave_shu " "Info: Found design unit 1: XIANSHI-behave_shu" {  } { { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 XIANSHI " "Info: Found entity 1: XIANSHI" {  } { { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FENPIN.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file FENPIN.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FENPIN-BEHAVE " "Info: Found design unit 1: FENPIN-BEHAVE" {  } { { "FENPIN.vhd" "" { Text "F:/数字频率计1/FENPIN.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 FENPIN " "Info: Found entity 1: FENPIN" {  } { { "FENPIN.vhd" "" { Text "F:/数字频率计1/FENPIN.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "F " "Info: Elaborating entity \"F\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "XIANSHI XIANSHI:inst3 " "Info: Elaborating entity \"XIANSHI\" for hierarchy \"XIANSHI:inst3\"" {  } { { "F.bdf" "inst3" { Schematic "F:/数字频率计1/F.bdf" { { -16 632 848 112 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "RST xiANshi.vhd(40) " "Warning (10492): VHDL Process Statement warning at xiANshi.vhd(40): signal \"RST\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 40 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "en_xhdl3 xiANshi.vhd(68) " "Warning (10492): VHDL Process Statement warning at xiANshi.vhd(68): signal \"en_xhdl3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 68 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "DATAIN xiANshi.vhd(70) " "Warning (10492): VHDL Process Statement warning at xiANshi.vhd(70): signal \"DATAIN\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 70 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "DATAIN xiANshi.vhd(72) " "Warning (10492): VHDL Process Statement warning at xiANshi.vhd(72): signal \"DATAIN\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "xiANshi.vhd" "" { Text "F:/数字频率计1/xiANshi.vhd" 72 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}