plj.fit.qmsg

基于CPLD的数字频率计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jan 10 14:37:14 2009 " "Info: Processing started: Sat Jan 10 14:37:14 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off plj -c plj " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off plj -c plj" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "plj EPM1270GT144C5 " "Info: Selected device EPM1270GT144C5 for design \"plj\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570GT144C5 " "Info: Device EPM570GT144C5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570GT144I5 " "Info: Device EPM570GT144I5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270GT144I5 " "Info: Device EPM1270GT144I5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tsu 2.0 ns " "Info: Assuming a global tsu requirement of 2.0 ns" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tco 1.0 ns " "Info: Assuming a global tco requirement of 1.0 ns" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tpd 1.0 ns " "Info: Assuming a global tpd requirement of 1.0 ns" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLKIN Global clock " "Info: Automatically promoted signal \"CLKIN\" to use Global clock" {  } { { "F.bdf" "" { Schematic "F:/数字频率计1/F.bdf" { { -456 48 216 -440 "CLKIN" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "CLKIN " "Info: Pin \"CLKIN\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "F.bdf" "" { Schematic "F:/数字频率计1/F.bdf" { { -456 48 216 -440 "CLKIN" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLKIN" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "plj" "UNKNOWN" "V1" "F:/数字频率计1/db/plj.quartus_db" { Floorplan "F:/数字频率计1/" "" "" { CLKIN } "NODE_NAME" } "" } } { "F:/数字频率计1/plj.fld" "" { Floorplan "F:/数字频率计1/plj.fld" "" "" { CLKIN } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "TESTCTL:inst17\|DIV2CLK Global clock " "Info: Automatically promoted some destinations of signal \"TESTCTL:inst17\|DIV2CLK\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "TESTCTL:inst17\|DIV2CLK " "Info: Destination \"TESTCTL:inst17\|DIV2CLK\" may be non-global or may not use global clock" {  } { { "TESTCTL.vhd" "" { Text "F:/数字频率计1/TESTCTL.vhd" 30 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CNT10:inst10\|CQI\[3\] " "Info: Destination \"CNT10:inst10\|CQI\[3\]\" may be non-global or may not use global clock" {  } { { "CNT10.vhd" "" { Text "F:/数字频率计1/CNT10.vhd" 16 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CNT10:inst10\|CQI\[0\] " "Info: Destination \"CNT10:inst10\|CQI\[0\]\" may be non-global or may not use global clock" {  } { { "CNT10.vhd" "" { Text "F:/数字频率计1/CNT10.vhd" 16 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CNT10:inst10\|CQI\[2\] " "Info: Destination \"CNT10:inst10\|CQI\[2\]\" may be non-global or may not use global clock" {  } { { "CNT10.vhd" "" { Text "F:/数字频率计1/CNT10.vhd" 16 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CNT10:inst10\|CQI\[1\] " "Info: Destination \"CNT10:inst10\|CQI\[1\]\" may be non-global or may not use global clock" {  } { { "CNT10.vhd" "" { Text "F:/数字频率计1/CNT10.vhd" 16 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CNT10:inst\|CQI\[0\] " "Info: Destination \"CNT10:inst\|CQI\[0\]\" may be non-global or may not use global clock" {  } { { "CNT10.vhd" "" { Text "F:/数字频率计1/CNT10.vhd" 16 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CNT10:inst9\|CQI\[3\] " "Info: Destination \"CNT10:inst9\|CQI\[3\]\" may be non-global or may not use global clock" {  } { { "CNT10.vhd" "" { Text "F:/数字频率计1/CNT10.vhd" 16 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CNT10:inst9\|CQI\[0\] " "Info: Destination \"CNT10:inst9\|CQI\[0\]\" may be non-global or may not use global clock" {  } { { "CNT10.vhd" "" { Text "F:/数字频率计1/CNT10.vhd" 16 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CNT10:inst9\|CQI\[2\] " "Info: Destination \"CNT10:inst9\|CQI\[2\]\" may be non-global or may not use global clock" {  } { { "CNT10.vhd" "" { Text "F:/数字频率计1/CNT10.vhd" 16 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CNT10:inst9\|CQI\[1\] " "Info: Destination \"CNT10:inst9\|CQI\[1\]\" may be non-global or may not use global clock" {  } { { "CNT10.vhd" "" { Text "F:/数字频率计1/CNT10.vhd" 16 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0 0 "Limited to %1!d! non-global destinations" 0 0}  } { { "TESTCTL.vhd" "" { Text "F:/数字频率计1/TESTCTL.vhd" 30 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLK Global clock " "Info: Automatically promoted signal \"CLK\" to use Global clock" {  } { { "F.bdf" "" { Schematic "F:/数字频率计1/F.bdf" { { -504 200 368 -488 "CLK" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "CLK " "Info: Pin \"CLK\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "F.bdf" "" { Schematic "F:/数字频率计1/F.bdf" { { -504 200 368 -488 "CLK" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "plj" "UNKNOWN" "V1" "F:/数字频率计1/db/plj.quartus_db" { Floorplan "F:/数字频率计1/" "" "" { CLK } "NODE_NAME" } "" } } { "F:/数字频率计1/plj.fld" "" { Floorplan "F:/数字频率计1/plj.fld" "" "" { CLK } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "rtl~876 Global clock " "Info: Automatically promoted signal \"rtl~876\" to use Global clock" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~876" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "plj" "UNKNOWN" "V1" "F:/数字频率计1/db/plj.quartus_db" { Floorplan "F:/数字频率计1/" "" "" { rtl~876 } "NODE_NAME" } "" } } { "F:/数字频率计1/plj.fld" "" { Floorplan "F:/数字频率计1/plj.fld" "" "" { rtl~876 } "NODE_NAME" } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}