plj.map.summary

基于CPLD的数字频率计

Analysis & Synthesis Status : Successful - Sat Jan 10 14:37:13 2009
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : plj
Top-level Entity Name : F
Family : MAX II
Total logic elements : 310
Total pins : 20
Total virtual pins : 0
UFM blocks : 0