fenpin.vhd

来自「基于CPLD的数字频率计」· VHDL 代码 · 共 27 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY FENPIN IS
  PORT(
         CLK: IN STD_LOGIC;
         RST: IN STD_LOGIC;
         CLK2,CLK4,CLK8,CLK16,CLKX:OUT STD_LOGIC
        );
 END FENPIN;
ARCHITECTURE BEHAVE OF FENPIN IS
  SIGNAL TEMP :STD_LOGIC_VECTOR(100 DOWNTO 0);
  BEGIN
PROCESS(CLK)IS
  BEGIN
 IF CLK'EVENT AND CLK='1' THEN
           TEMP <=TEMP + 1;
       END IF;
     
   END PROCESS;
    CLK2<=TEMP(0);
    CLK4<=TEMP(1);
    CLK8<=TEMP(2);
    CLK16<=TEMP(3);
    CLKX<=TEMP(7);
END BEHAVE;