testctl.vhd

来自「基于CPLD的数字频率计」· VHDL 代码 · 共 45 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;    		--测频控制信号发生器
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TESTCTL IS 
    PORT (CLKIN:IN STD_LOGIC;    		--1 Hz测频控制时钟
          TSTEN:OUT STD_LOGIC;    	--计数器时钟使能
          CLR_CNT:OUT STD_LOGIC;    	--计数器清零
          LOAD:OUT STD_LOGIC);    	--输出锁存信号
END TESTCTL; 
 ARCHITECTURE ART OF TESTCTL IS 
     SIGNAL DIV2CLK :STD_LOGIC;
     SIGNAL CLK2    : STD_LOGIC;
     SIGNAL COUNT_SIGNAL1 :INTEGER RANGE 1 TO 200000000;
     BEGIN

PROCESS(CLKIN)
    BEGIN
       IF(CLKIN'EVENT AND CLKIN='1') THEN
         IF COUNT_SIGNAL1 =20000000 THEN  --40MHZ时钟分为1HZ
              COUNT_SIGNAL1 <= 1 ;
               CLK2<= NOT CLK2 ;
                 ELSE
                   COUNT_SIGNAL1<=COUNT_SIGNAL1+1;
              END IF;
             END IF;
           END PROCESS;

PROCESS ( CLKIN )
BEGIN
IF  CLK2'EVENT AND CLK2= '1' THEN     		--1 Hz时钟二分频
     Div2CLK<=NOT Div2CLK;
  END IF ;
END PROCESS; 
 PROCESS ( CLK2,Div2CLK )
BEGIN 
     IF CLK2= '0' AND Div2CLK = '0' THEN         	--产生计数器清零信号
     CLR_CNT<= '1';
     ELSE CLR_CNT<= '0' ;    
   END IF;
  END PROCESS;
  LOAD<=NOT Div2CLK;  
  TSTEN<=Div2CLK;
END ART;