kz.vhd

来自「基于CPLD的数字频率计」· VHDL 代码 · 共 35 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;    		--测频控制信号发生器
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY KZ IS
 PORT( 
      datain1:   in std_logic_vector(3 downto 0);
      datain2:   in std_logic_vector(3 downto 0);
      datain3:   in std_logic_vector(3 downto 0);
      datain4:   in std_logic_vector(3 downto 0);
      datain5:   in std_logic_vector(3 downto 0);
      datain6:   in std_logic_vector(3 downto 0);
      datain7:   in std_logic_vector(3 downto 0);
      datain8:   in std_logic_vector(3 downto 0);
      clk    :   in std_logic;
      k      :   in std_logic;
      dataout:   out std_logic_vector(31 downto 0)
                                                 );
  end kz;

architecture  behave of kz is
  signal dataout_buff :std_logic_vector(31 downto 0);
  begin
   dataout<=dataout_buff;
  process(clk)
    begin
    if clk'event and clk='1' then
       if(k='0') then
        dataout_buff<=datain1&datain2&datain3&datain4&datain5&datain6&datain7&datain8;
          else 
              dataout_buff<="00000000000000000000000000000000";
         end if;
    end if;
  end process;
end behave;