reg32b.vhd

来自「基于CPLD的数字频率计」· VHDL 代码 · 共 21 行

LIBRARY IEEE;    --32位锁存器
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG32B IS 
  PORT(LOAD:IN STD_LOGIC;
       DIN:IN STD_LOGIC_VECTOR(31 DOWNTO 0);
       KK   : IN STD_LOGIC;
       DOUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END REG32B;
ARCHITECTURE ART OF REG32B IS 
 BEGIN
  PROCESS ( LOAD, DIN ) IS
      BEGIN
        IF LOAD 'EVENT AND LOAD= '1' THEN 
           IF(KK='0') THEN
             DOUT<=DIN;       --锁存输入数据
         END IF;
      END IF ;
   END PROCESS;
END ART;