📄 plj.map.rpt
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; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 52 ;
; ; ;
; Total registers ; 178 ;
; Total logic cells in carry chains ; 40 ;
; I/O pins ; 20 ;
; Maximum fan-out node ; CLKIN ;
; Maximum fan-out ; 113 ;
; Total fan-out ; 1117 ;
; Average fan-out ; 3.38 ;
+---------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |F ; 310 (39) ; 178 ; 0 ; 20 ; 0 ; 132 (39) ; 54 (0) ; 124 (0) ; 40 (0) ; 0 (0) ; |F ;
; |CNT10:inst10| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |F|CNT10:inst10 ;
; |CNT10:inst4| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |F|CNT10:inst4 ;
; |CNT10:inst5| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |F|CNT10:inst5 ;
; |CNT10:inst6| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |F|CNT10:inst6 ;
; |CNT10:inst7| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |F|CNT10:inst7 ;
; |CNT10:inst8| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |F|CNT10:inst8 ;
; |CNT10:inst9| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |F|CNT10:inst9 ;
; |CNT10:inst| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |F|CNT10:inst ;
; |KZ:inst1| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 30 (30) ; 0 (0) ; 0 (0) ; |F|KZ:inst1 ;
; |REG32B:inst2| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 (0) ; 32 (32) ; 0 (0) ; 0 (0) ; 0 (0) ; |F|REG32B:inst2 ;
; |TESTCTL:inst17| ; 59 (59) ; 30 ; 0 ; 0 ; 0 ; 29 (29) ; 20 (20) ; 10 (10) ; 28 (28) ; 0 (0) ; |F|TESTCTL:inst17 ;
; |XIANSHI:inst3| ; 116 (116) ; 52 ; 0 ; 0 ; 0 ; 64 (64) ; 0 (0) ; 52 (52) ; 12 (12) ; 0 (0) ; |F|XIANSHI:inst3 ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 178 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 52 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 64 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; XIANSHI:inst3|en_xhdl3[7] ; 19 ;
; XIANSHI:inst3|en_xhdl3[6] ; 16 ;
; XIANSHI:inst3|en_xhdl3[5] ; 13 ;
; XIANSHI:inst3|en_xhdl3[4] ; 15 ;
; XIANSHI:inst3|en_xhdl3[3] ; 12 ;
; XIANSHI:inst3|en_xhdl3[2] ; 12 ;
; XIANSHI:inst3|en_xhdl3[1] ; 8 ;
; Total number of inverted registers = 7 ; ;
+----------------------------------------+---------+
+------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------+
; 9:1 ; 7 bits ; 42 LEs ; 35 LEs ; 7 LEs ; Yes ; |F|XIANSHI:inst3|en_xhdl3[7] ;
; 256:1 ; 4 bits ; 680 LEs ; 36 LEs ; 644 LEs ; No ; |F|XIANSHI:inst3|seg_data_buf[2] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/数字频率计1/plj.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Sat Jan 10 14:37:06 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off plj -c plj
Info: Found 2 design units, including 1 entities, in source file CNT10.vhd
Info: Found design unit 1: CNT10-ART
Info: Found entity 1: CNT10
Info: Found 2 design units, including 1 entities, in source file REG32B.vhd
Info: Found design unit 1: REG32B-ART
Info: Found entity 1: REG32B
Info: Found 2 design units, including 1 entities, in source file TESTCTL.vhd
Info: Found design unit 1: TESTCTL-ART
Info: Found entity 1: TESTCTL
Info: Found 2 design units, including 1 entities, in source file FREQ.vhd
Info: Found design unit 1: FREQ-ART
Info: Found entity 1: FREQ
Info: Found 1 design units, including 1 entities, in source file F.bdf
Info: Found entity 1: F
Info: Found 2 design units, including 1 entities, in source file kz.vhd
Info: Found design unit 1: kz-behave
Info: Found entity 1: KZ
Warning: Can't analyze file -- file F:/数字频率计1/xinashi.vhd is missing
Info: Found 2 design units, including 1 entities, in source file xiANshi.vhd
Info: Found design unit 1: XIANSHI-behave_shu
Info: Found entity 1: XIANSHI
Info: Found 2 design units, including 1 entities, in source file FENPIN.vhd
Info: Found design unit 1: FENPIN-BEHAVE
Info: Found entity 1: FENPIN
Info: Elaborating entity "F" for the top level hierarchy
Info: Elaborating entity "XIANSHI" for hierarchy "XIANSHI:inst3"
Warning (10492): VHDL Process Statement warning at xiANshi.vhd(40): signal "RST" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at xiANshi.vhd(68): signal "en_xhdl3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at xiANshi.vhd(70): signal "DATAIN" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at xiANshi.vhd(72): signal "DATAIN" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at xiANshi.vhd(74): signal "DATAIN" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at xiANshi.vhd(76): signal "DATAIN" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at xiANshi.vhd(78): signal "DATAIN" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at xiANshi.vhd(80): signal "DATAIN" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at xiANshi.vhd(82): signal "DATAIN" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at xiANshi.vhd(84): signal "DATAIN" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info (10425): VHDL Case Statement information at xiANshi.vhd(126): OTHERS choice is never selected
Info: Elaborating entity "REG32B" for hierarchy "REG32B:inst2"
Info: Elaborating entity "TESTCTL" for hierarchy "TESTCTL:inst17"
Warning (10492): VHDL Process Statement warning at TESTCTL.vhd(30): signal "CLK2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "CNT10" for hierarchy "CNT10:inst10"
Info: Elaborating entity "KZ" for hierarchy "KZ:inst1"
Warning: Output pins are stuck at VCC or GND
Warning: Pin "SEG_DATA[0]" stuck at VCC
Info: Registers with preset signals will power-up high
Info: Implemented 330 device resources after synthesis - the final resource count might be different
Info: Implemented 4 input pins
Info: Implemented 16 output pins
Info: Implemented 310 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 14 warnings
Info: Processing ended: Sat Jan 10 14:37:12 2009
Info: Elapsed time: 00:00:06
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