plj.fit.talkback.xml

基于CPLD的数字频率计

<!--
This XML file (created on Mon Oct 27 21:45:00 2008) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>6.0</ver>
<schema>quartus_version_6.0_build_178.xsd</schema>
<license>
	<host_id>00e0a00ac597</host_id>
	<nic_id>00e0a00ac597</nic_id>
	<cdrive_id>80087eed</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>6.0</version>
	<build>Build 178</build>
	<binary_type>32</binary_type>
	<module>quartus_fit</module>
	<edition>Full Version</edition>
	<eval>Licensed</eval>
	<compilation_end_time>Mon Oct 27 21:45:00 2008</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">1607</cpu_freq>
	</cpu>
	<ram units="MB">512</ram>
</machine>
<project>F:/数字频率计1/plj</project>
<revision>plj</revision>
<compilation_summary>
	<flow_status>Successful - Mon Oct 27 21:45:00 2008</flow_status>
	<quartus_ii_version>6.0 Build 178 04/27/2006 SJ Full Version</quartus_ii_version>
	<revision_name>plj</revision_name>
	<top_level_entity_name>F</top_level_entity_name>
	<family>MAX II</family>
	<device>EPM1270GT144C5</device>
	<timing_models>Final</timing_models>
	<met_timing_requirements>N/A</met_timing_requirements>
	<total_logic_elements>297 / 1,270 ( 23 % )</total_logic_elements>
	<total_pins>19 / 116 ( 16 % )</total_pins>
	<total_virtual_pins>0</total_virtual_pins>
	<ufm_blocks>0 / 1 ( 0 % )</ufm_blocks>
</compilation_summary>
<resource_usage_summary>
	<rsc name="Total logic elements" util="23" max=" 1270 " type="int">297 </rsc>
	<rsc name="-- Combinational with no register" type="int">119</rsc>
	<rsc name="-- Register only" type="int">46</rsc>
	<rsc name="-- Combinational with a register" type="int">132</rsc>
	<rsc name="Logic element usage by number of LUT inputs" type="text"></rsc>
	<rsc name="-- 4 input functions" type="int">101</rsc>
	<rsc name="-- 3 input functions" type="int">26</rsc>
	<rsc name="-- 2 input functions" type="int">120</rsc>
	<rsc name="-- 1 input functions" type="int">31</rsc>
	<rsc name="-- 0 input functions" type="int">19</rsc>
	<rsc name="Logic elements by mode" type="text"></rsc>
	<rsc name="-- normal mode" type="int">260</rsc>
	<rsc name="-- arithmetic mode" type="int">37</rsc>
	<rsc name="-- qfbk mode" type="int">7</rsc>
	<rsc name="-- register cascade mode" type="int">0</rsc>
	<rsc name="-- synchronous clear/load mode" type="int">26</rsc>
	<rsc name="-- asynchronous clear/load mode" type="int">52</rsc>
	<rsc name="Total LABs" util="32" max=" 127 " type="int">41 </rsc>
	<rsc name="Logic elements in carry chains" type="int">39</rsc>
	<rsc name="User inserted logic elements" type="int">0</rsc>
	<rsc name="Virtual pins" type="int">0</rsc>
	<rsc name="I/O pins" util="16" max=" 116 " type="int">19 </rsc>
	<rsc name="-- Clock pins" util="--" max=" 0 " type="int">0 </rsc>
	<rsc name="Global signals" type="int">4</rsc>
	<rsc name="UFM blocks" util="0" max=" 1 " type="int">0 </rsc>
	<rsc name="Global clocks" util="100" max=" 4 " type="int">4 </rsc>
	<rsc name="Maximum fan-out node" type="text">CLKIN</rsc>
	<rsc name="Maximum fan-out" type="int">113</rsc>
	<rsc name="Highest non-global fan-out signal" type="text">CNT10:inst10|Equal0~29</rsc>
	<rsc name="Highest non-global fan-out" type="int">60</rsc>
	<rsc name="Total fan-out" type="int">1104</rsc>
	<rsc name="Average fan-out" type="float">3.49</rsc>
</resource_usage_summary>
<control_signals>
	<row>
		<name>TESTCTL:inst17|DIV2CLK</name>
		<location>LC_X12_Y3_N2</location>
		<fan_out>66</fan_out>
		<usage>Clock, Clock enable</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK0</global_line_name>
	</row>
	<row>
		<name>TESTCTL:inst17|CLK2</name>
		<location>LC_X12_Y4_N7</location>
		<fan_out>3</fan_out>
		<usage>Clock</usage>
		<global>no</global>
	</row>
	<row>
		<name>CNT10:inst9|Equal0~29</name>
		<location>LC_X13_Y9_N0</location>
		<fan_out>4</fan_out>
		<usage>Clock</usage>
		<global>no</global>
	</row>
	<row>
		<name>TESTCTL:inst17|COUNT_SIGNAL1[7]</name>
		<location>LC_X8_Y7_N0</location>
		<fan_out>5</fan_out>
		<usage>Clock</usage>
		<global>no</global>
	</row>
	<row>
		<name>CNT10:inst8|Equal0~29</name>
		<location>LC_X15_Y9_N0</location>
		<fan_out>4</fan_out>
		<usage>Clock</usage>
		<global>no</global>
	</row>
	<row>
		<name>CNT10:inst5|Equal0~29</name>
		<location>LC_X11_Y5_N5</location>
		<fan_out>4</fan_out>
		<usage>Clock</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK2</global_line_name>
	</row>
	<row>
		<name>CNT10:inst7|Equal0~29</name>
		<location>LC_X15_Y8_N4</location>
		<fan_out>4</fan_out>
		<usage>Clock</usage>
		<global>no</global>
	</row>
	<row>
		<name>CNT10:inst6|Equal0~29</name>
		<location>LC_X13_Y8_N0</location>
		<fan_out>4</fan_out>
		<usage>Clock</usage>
		<global>no</global>
	</row>
	<row>
		<name>CNT10:inst|Equal0~29</name>
		<location>LC_X12_Y5_N5</location>
		<fan_out>4</fan_out>
		<usage>Clock</usage>
		<global>no</global>
	</row>
	<row>
		<name>CNT10:inst4|Equal0~29</name>
		<location>LC_X13_Y6_N9</location>
		<fan_out>4</fan_out>
		<usage>Clock</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK1</global_line_name>
	</row>
	<row>
		<name>CLKIN</name>
		<location>PIN_127</location>
		<fan_out>113</fan_out>
		<usage>Clock</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK3</global_line_name>
	</row>
</control_signals>
<non_global_high_fan_out_signals>
	<row>
		<name>XIANSHI:inst3|en_xhdl3[7]</name>
		<fan_out>20</fan_out>
	</row>
	<row>
		<name>XIANSHI:inst3|en_xhdl3[6]</name>
		<fan_out>17</fan_out>
	</row>
	<row>
		<name>XIANSHI:inst3|en_xhdl3[5]</name>
		<fan_out>14</fan_out>
	</row>
	<row>
		<name>XIANSHI:inst3|en_xhdl3[4]</name>
		<fan_out>9</fan_out>
	</row>
	<row>
		<name>XIANSHI:inst3|en_xhdl3[3]</name>
		<fan_out>17</fan_out>
	</row>
	<row>
		<name>XIANSHI:inst3|en_xhdl3[2]</name>
		<fan_out>12</fan_out>
	</row>
	<row>
		<name>XIANSHI:inst3|en_xhdl3[1]</name>
		<fan_out>8</fan_out>
	</row>
	<row>
		<name>XIANSHI:inst3|en_xhdl3[0]</name>
		<fan_out>13</fan_out>
	</row>
	<row>
		<name>XIANSHI:inst3|DATAIN[29]</name>
		<fan_out>1</fan_out>
	</row>
	<row>
		<name>XIANSHI:inst3|Mux3~788</name>
		<fan_out>8</fan_out>
	</row>
</non_global_high_fan_out_signals>
<interconnect_usage_summary>
	<rsc name="Local interconnects" util="9" max=" 3938 " type="int">353 </rsc>
	<rsc name="LUT chains" util="1" max=" 1143 " type="int">13 </rsc>
	<rsc name="R4s" util="6" max=" 2832 " type="int">170 </rsc>
	<rsc name="C4s" util="7" max=" 2870 " type="int">203 </rsc>
	<rsc name="Global clocks" util="100" max=" 4 " type="int">4 </rsc>
	<rsc name="LAB clocks" util="24" max=" 72 " type="int">17 </rsc>
	<rsc name="Direct links" util="2" max=" 3938 " type="int">67 </rsc>
</interconnect_usage_summary>
<mep_data>
	<command_line>quartus_fit --read_settings_files=off --write_settings_files=off plj -c plj</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results</warning>
	<warning>Warning: Ignored locations or region assignments to the following nodes</warning>
	<warning>Warning: Node &quot;CLK&quot; is assigned to location or region, but does not exist in design</warning>
	<info>Info: Generated suppressed messages file F:/数字频率计1/plj.fit.smsg</info>
	<info>Info: Quartus II Fitter was successful. 0 errors, 3 warnings</info>
	<info>Info: Elapsed time: 00:00:05</info>
	<info>Info: Processing ended: Mon Oct 27 21:45:00 2008</info>
	<info>Info: Pin SEG_DATA[0] has VCC driving its datain port</info>
</messages>
<fitter_settings>
	<row>
		<option>Device</option>
		<setting>EPM1270GT144C5</setting>
	</row>
	<row>
		<option>Use smart compilation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Router Timing Optimization Level</option>
		<setting>Normal</setting>
		<default_value>Normal</default_value>
	</row>
	<row>
		<option>Placement Effort Multiplier</option>
		<setting>1.0</setting>
		<default_value>1.0</default_value>
	</row>
	<row>
		<option>Router Effort Multiplier</option>
		<setting>1.0</setting>
		<default_value>1.0</default_value>
	</row>
	<row>
		<option>Optimize Hold Timing</option>
		<setting>IO Paths and Minimum TPD Paths</setting>
		<default_value>IO Paths and Minimum TPD Paths</default_value>
	</row>
	<row>
		<option>Optimize Fast-Corner Timing</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Guarantee I/O Paths Have Zero Hold Time at Fast Corner</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>PowerPlay Power Optimization</option>
		<setting>Normal compilation</setting>
		<default_value>Normal compilation</default_value>
	</row>
	<row>
		<option>Optimize Timing</option>
		<setting>Normal compilation</setting>
		<default_value>Normal compilation</default_value>
	</row>
	<row>
		<option>Optimize IOC Register Placement for Timing</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Limit to One Fitting Attempt</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Final Placement Optimizations</option>
		<setting>Automatically</setting>
		<default_value>Automatically</default_value>
	</row>
	<row>
		<option>Fitter Aggressive Routability Optimizations</option>
		<setting>Automatically</setting>
		<default_value>Automatically</default_value>
	</row>
	<row>
		<option>Fitter Initial Placement Seed</option>
		<setting>1</setting>
		<default_value>1</default_value>
	</row>
	<row>
		<option>Slow Slew Rate</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>PCI I/O</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Weak Pull-Up Resistor</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Enable Bus-Hold Circuitry</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto Delay Chains</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Perform Physical Synthesis for Combinational Logic</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Perform Register Duplication</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Perform Register Retiming</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Perform Asynchronous Signal Pipelining</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Fitter Effort</option>
		<setting>Auto Fit</setting>
		<default_value>Auto Fit</default_value>
	</row>
	<row>
		<option>Physical Synthesis Effort Level</option>