📄 cun1.rpt
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Project Information e:\vhdcx\cun1.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 10/30/2008 09:20:12
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
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under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
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limited to modification, reverse engineering, de-compiling, or use with
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the intellectual property, including patents, copyrights, trademarks,
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***** Project compilation was successful
CUN1
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
cun1 EPM7032LC44-6 7 8 0 19 8 59 %
User Pins: 7 8 0
Project Information e:\vhdcx\cun1.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'CPC' chosen for auto global Clock
Device-Specific Information: e:\vhdcx\cun1.rpt
cun1
***** Logic for device 'cun1' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
R
E
S
E
R
I I I V G G G C G V
D D D C N N N P N N E
3 4 5 C D D D C D 7 D
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
ID2 | 7 39 | RESERVED
ID1 | 8 38 | RESERVED
ID0 | 9 37 | RESERVED
GND | 10 36 | RESERVED
N0 | 11 35 | VCC
N5 | 12 EPM7032LC44-6 34 | RESERVED
RESERVED | 13 33 | RESERVED
RESERVED | 14 32 | RESERVED
VCC | 15 31 | N6
RESERVED | 16 30 | GND
RESERVED | 17 29 | N3
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V N N R R N
E E E E N C 2 1 E E 4
S S S S D C S S
E E E E E E
R R R R R R
V V V V V V
E E E E E E
D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\vhdcx\cun1.rpt
cun1
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 3/16( 18%) 8/16( 50%) 6/16( 37%) 7/36( 19%)
B: LC17 - LC32 16/16(100%) 6/16( 37%) 13/16( 81%) 16/36( 44%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 14/32 ( 43%)
Total logic cells used: 19/32 ( 59%)
Total shareable expanders used: 8/32 ( 25%)
Total Turbo logic cells used: 19/32 ( 59%)
Total shareable expanders not available (n/a): 11/32 ( 34%)
Average fan-in: 6.05
Total fan-in: 115
Total input pins required: 7
Total output pins required: 8
Total bidirectional pins required: 0
Total logic cells required: 19
Total flipflops required: 8
Total product terms required: 81
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 8
Synthesized logic cells: 11/ 32 ( 34%)
Device-Specific Information: e:\vhdcx\cun1.rpt
cun1
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
43 - - INPUT G 0 0 0 0 0 0 0 CPC
9 (6) (A) INPUT 0 0 0 0 0 5 10 ID0
8 (5) (A) INPUT 0 0 0 0 0 5 10 ID1
7 (4) (A) INPUT 0 0 0 0 0 4 11 ID2
6 (3) (A) INPUT 0 0 0 0 0 6 10 ID3
5 (2) (A) INPUT 0 0 0 0 0 6 11 ID4
4 (1) (A) INPUT 0 0 0 0 0 8 9 ID5
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\vhdcx\cun1.rpt
cun1
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
11 7 A FF + t 4 0 1 6 0 0 0 N0 (:23)
25 31 B FF + t 5 2 1 6 2 0 0 N1 (:22)
24 32 B FF + t 0 0 0 1 3 0 0 N2 (:21)
29 27 B FF + t 1 1 0 5 3 0 0 N3 (:20)
28 28 B FF + t 0 0 0 1 2 0 0 N4 (:19)
12 8 A FF + t 1 0 0 3 1 0 0 N5 (:18)
31 26 B FF + t 2 1 1 6 1 0 0 N6 (:17)
41 17 B FF + t 0 0 0 6 0 0 0 N7 (:16)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\vhdcx\cun1.rpt
cun1
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(40) 18 B SOFT s t 1 0 1 6 0 1 0 ~3944~1
(4) 1 A SOFT s t 1 0 1 5 0 1 0 ~3950~1
(39) 19 B SOFT s t 1 0 1 6 0 1 0 ~3962~1
(38) 20 B SOFT s t 0 0 0 4 0 2 0 ~3962~2
(37) 21 B SOFT s t 1 0 1 6 0 1 0 ~3968~1
(36) 22 B SOFT s t 1 0 1 6 0 1 0 ~3968~2
(34) 23 B SOFT s t 0 0 0 4 0 1 0 ~3968~3
(33) 24 B SOFT s t 1 0 1 6 0 1 0 ~3974~1
(32) 25 B SOFT s t 0 0 0 6 0 1 0 ~3974~2
(27) 29 B SOFT s t 1 0 1 6 0 1 0 ~3980~1
(26) 30 B SOFT s t 1 0 1 6 0 1 0 ~3980~2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\vhdcx\cun1.rpt
cun1
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----- LC7 N0
| +--- LC8 N5
| | +- LC1 ~3950~1
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'A'
LC | | | | A B | Logic cells that feed LAB 'A':
Pin
43 -> - - - | - - | <-- CPC
9 -> * - - | * * | <-- ID0
8 -> * - * | * * | <-- ID1
7 -> * - * | * * | <-- ID2
6 -> * * * | * * | <-- ID3
5 -> * * * | * * | <-- ID4
4 -> * * * | * * | <-- ID5
LC18 -> - * - | * - | <-- ~3944~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\vhdcx\cun1.rpt
cun1
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC31 N1
| +----------------------------- LC32 N2
| | +--------------------------- LC27 N3
| | | +------------------------- LC28 N4
| | | | +----------------------- LC26 N6
| | | | | +--------------------- LC17 N7
| | | | | | +------------------- LC18 ~3944~1
| | | | | | | +----------------- LC19 ~3962~1
| | | | | | | | +--------------- LC20 ~3962~2
| | | | | | | | | +------------- LC21 ~3968~1
| | | | | | | | | | +----------- LC22 ~3968~2
| | | | | | | | | | | +--------- LC23 ~3968~3
| | | | | | | | | | | | +------- LC24 ~3974~1
| | | | | | | | | | | | | +----- LC25 ~3974~2
| | | | | | | | | | | | | | +--- LC29 ~3980~1
| | | | | | | | | | | | | | | +- LC30 ~3980~2
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC19 -> - - - * - - - - - - - - - - - - | - * | <-- ~3962~1
LC20 -> - * - * - - - - - - - - - - - - | - * | <-- ~3962~2
LC21 -> - - * - - - - - - - - - - - - - | - * | <-- ~3968~1
LC22 -> - - * - - - - - - - - - - - - - | - * | <-- ~3968~2
LC23 -> - - * - - - - - - - - - - - - - | - * | <-- ~3968~3
LC24 -> - * - - - - - - - - - - - - - - | - * | <-- ~3974~1
LC25 -> - * - - - - - - - - - - - - - - | - * | <-- ~3974~2
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