cun1.rpt
来自「基于vhdl的qpsk算法研究与性能测试」· RPT 代码 · 共 592 行 · 第 1/2 页
RPT
592 行
LC29 -> * - - - - - - - - - - - - - - - | - * | <-- ~3980~1
LC30 -> * - - - - - - - - - - - - - - - | - * | <-- ~3980~2
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- CPC
9 -> * - * - * * * * * * * * * * * * | * * | <-- ID0
8 -> * - * - * * * * - * * * * * * * | * * | <-- ID1
7 -> * - - - * * * * * * * * * * * * | * * | <-- ID2
6 -> * - * - * * * * * * * - * * * * | * * | <-- ID3
5 -> * - * - * * * * * * * * * * * * | * * | <-- ID4
4 -> * * * * * * * * - * * - * * * * | * * | <-- ID5
LC1 -> - - - - * - - - - - - - - - - - | - * | <-- ~3950~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\vhdcx\cun1.rpt
cun1
** EQUATIONS **
CPC : INPUT;
ID0 : INPUT;
ID1 : INPUT;
ID2 : INPUT;
ID3 : INPUT;
ID4 : INPUT;
ID5 : INPUT;
-- Node name is 'N0' = 'N0~58'
-- Equation name is 'N0', location is LC007, type is output.
N0 = DFFE( _EQ001 $ GND, GLOBAL( CPC), VCC, VCC, VCC);
_EQ001 = !ID0 & !ID1 & !ID2 & !ID3 & _X001
# ID0 & ID1 & !ID2 & ID4
# !ID0 & ID1 & ID3 & !ID4
# !ID0 & !ID3 & ID4 & _X002
# !ID1 & ID2 & !ID4 & _X003;
_X001 = EXP( ID4 & ID5);
_X002 = EXP(!ID1 & !ID2);
_X003 = EXP(!ID0 & !ID3);
-- Node name is 'N1' = 'N1~58'
-- Equation name is 'N1', location is LC031, type is output.
N1 = DFFE( _EQ002 $ _EQ003, GLOBAL( CPC), VCC, VCC, VCC);
_EQ002 = ID0 & !ID1 & ID3 & ID4 & !ID5
# ID2 & ID4 & !ID5 & _X004
# ID2 & ID3 & !ID5 & _X005
# !ID0 & !ID1 & ID2 & !ID5;
_X004 = EXP( ID0 & ID1 & !ID3);
_X005 = EXP( ID0 & ID1);
_EQ003 = !_LC029 & !_LC030 & _X006 & _X007;
_X006 = EXP( ID0 & ID1 & !ID3 & !ID4 & !ID5);
_X007 = EXP(!ID0 & !ID2 & ID4 & ID5);
-- Node name is 'N2' = 'N2~58'
-- Equation name is 'N2', location is LC032, type is output.
N2 = DFFE( _EQ004 $ !ID5, GLOBAL( CPC), VCC, VCC, VCC);
_EQ004 = !_LC020 & !_LC024 & !_LC025;
-- Node name is 'N3' = 'N3~58'
-- Equation name is 'N3', location is LC027, type is output.
N3 = DFFE( _EQ005 $ ID5, GLOBAL( CPC), VCC, VCC, VCC);
_EQ005 = !_LC021 & !_LC022 & !_LC023 & _X006;
_X006 = EXP( ID0 & ID1 & !ID3 & !ID4 & !ID5);
-- Node name is 'N4' = 'N4~58'
-- Equation name is 'N4', location is LC028, type is output.
N4 = DFFE( _EQ006 $ ID5, GLOBAL( CPC), VCC, VCC, VCC);
_EQ006 = !_LC019 & !_LC020;
-- Node name is 'N5' = 'N5~58'
-- Equation name is 'N5', location is LC008, type is output.
N5 = DFFE( _EQ007 $ !ID5, GLOBAL( CPC), VCC, VCC, VCC);
_EQ007 = !_LC018 & _X008;
_X008 = EXP(!ID3 & ID4);
-- Node name is 'N6' = 'N6~58'
-- Equation name is 'N6', location is LC026, type is output.
N6 = DFFE( _EQ008 $ _EQ009, GLOBAL( CPC), VCC, VCC, VCC);
_EQ008 = ID0 & ID1 & ID3 & ID4 & !ID5 & !_LC001 & _X007
# ID1 & !ID2 & !ID3 & !ID4 & !ID5 & !_LC001 & _X007
# ID0 & !ID2 & !ID3 & !ID4 & !ID5 & !_LC001 & _X007
# !ID1 & ID2 & !ID3 & !ID4 & !ID5 & !_LC001 & _X007;
_X007 = EXP(!ID0 & !ID2 & ID4 & ID5);
_EQ009 = !_LC001 & _X007;
_X007 = EXP(!ID0 & !ID2 & ID4 & ID5);
-- Node name is 'N7' = 'N7~58'
-- Equation name is 'N7', location is LC017, type is output.
N7 = DFFE( _EQ010 $ !ID5, GLOBAL( CPC), VCC, VCC, VCC);
_EQ010 = !ID0 & !ID1 & !ID2 & !ID3 & !ID4 & !ID5;
-- Node name is '~3944~1'
-- Equation name is '~3944~1', location is LC018, type is buried.
-- synthesized logic cell
_LC018 = LCELL( _EQ011 $ GND);
_EQ011 = !ID0 & !ID1 & !ID2 & !ID3 & !ID4 & !ID5
# ID0 & ID1 & !ID2
# ID0 & ID3 & !ID4
# ID1 & ID3 & !ID4
# !ID1 & ID2;
-- Node name is '~3950~1'
-- Equation name is '~3950~1', location is LC001, type is buried.
-- synthesized logic cell
_LC001 = LCELL( _EQ012 $ GND);
_EQ012 = ID1 & ID2 & !ID4 & ID5
# ID2 & ID3 & ID4 & !ID5
# !ID1 & !ID2 & ID4 & ID5
# !ID3 & ID4 & ID5
# ID3 & !ID4 & ID5;
-- Node name is '~3962~1'
-- Equation name is '~3962~1', location is LC019, type is buried.
-- synthesized logic cell
_LC019 = LCELL( _EQ013 $ GND);
_EQ013 = !ID1 & !ID2 & !ID3 & !ID4 & ID5
# ID0 & ID1 & ID2 & ID4
# !ID0 & ID1 & ID2 & !ID3
# !ID0 & ID1 & !ID2 & ID3
# ID0 & !ID1 & !ID2 & !ID4;
-- Node name is '~3962~2'
-- Equation name is '~3962~2', location is LC020, type is buried.
-- synthesized logic cell
_LC020 = LCELL( _EQ014 $ GND);
_EQ014 = ID0 & ID2 & ID3 & ID4
# ID0 & !ID2 & !ID3 & !ID4;
-- Node name is '~3968~1'
-- Equation name is '~3968~1', location is LC021, type is buried.
-- synthesized logic cell
_LC021 = LCELL( _EQ015 $ GND);
_EQ015 = ID0 & !ID1 & ID3 & ID4 & !ID5
# !ID0 & !ID1 & !ID2 & !ID3 & !ID4 & ID5
# ID0 & ID1 & ID2 & !ID3 & ID5
# ID0 & !ID1 & !ID2 & ID3 & ID5
# ID0 & ID1 & !ID2 & !ID4 & ID5;
-- Node name is '~3968~2'
-- Equation name is '~3968~2', location is LC022, type is buried.
-- synthesized logic cell
_LC022 = LCELL( _EQ016 $ GND);
_EQ016 = !ID0 & ID1 & !ID2 & ID3 & ID4
# ID0 & ID2 & !ID3 & ID4 & !ID5
# !ID0 & ID2 & !ID3 & !ID4 & ID5
# ID0 & !ID2 & ID3 & !ID4 & !ID5
# ID1 & ID2 & !ID3 & !ID4 & !ID5;
-- Node name is '~3968~3'
-- Equation name is '~3968~3', location is LC023, type is buried.
-- synthesized logic cell
_LC023 = LCELL( _EQ017 $ GND);
_EQ017 = !ID1 & ID2 & ID4
# !ID0 & !ID1 & ID2;
-- Node name is '~3974~1'
-- Equation name is '~3974~1', location is LC024, type is buried.
-- synthesized logic cell
_LC024 = LCELL( _EQ018 $ GND);
_EQ018 = ID0 & !ID1 & ID2 & !ID3 & !ID4 & ID5
# ID0 & ID1 & ID3 & ID4 & ID5
# ID0 & !ID1 & !ID2 & !ID3 & ID5
# ID0 & ID1 & ID2 & ID3
# !ID0 & ID1 & ID2 & !ID4;
-- Node name is '~3974~2'
-- Equation name is '~3974~2', location is LC025, type is buried.
-- synthesized logic cell
_LC025 = LCELL( _EQ019 $ GND);
_EQ019 = !ID0 & ID1 & !ID2 & ID4
# !ID0 & ID2 & ID3 & !ID4
# !ID0 & !ID1 & !ID3 & ID4
# !ID1 & !ID2 & !ID3 & !ID5;
-- Node name is '~3980~1'
-- Equation name is '~3980~1', location is LC029, type is buried.
-- synthesized logic cell
_LC029 = LCELL( _EQ020 $ GND);
_EQ020 = !ID0 & ID1 & ID2 & !ID4 & ID5
# ID0 & !ID2 & !ID3 & !ID4 & !ID5
# ID1 & !ID3 & ID4 & ID5
# ID2 & ID3 & !ID4 & ID5
# !ID2 & !ID3 & ID4 & ID5;
-- Node name is '~3980~2'
-- Equation name is '~3980~2', location is LC030, type is buried.
-- synthesized logic cell
_LC030 = LCELL( _EQ021 $ GND);
_EQ021 = !ID0 & !ID3 & ID4 & ID5
# !ID1 & ID3 & !ID4 & ID5
# !ID0 & ID3 & !ID4 & ID5
# ID1 & !ID2 & !ID3 & ID4
# ID1 & !ID2 & !ID4 & !ID5;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\vhdcx\cun1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 19,085K
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