📄 fpgd.rpt
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-- Equation name is '_LC062', type is buried
_LC062 = LCELL( _LC050 $ _EQ018);
_EQ018 = _LC049 & _LC054 & _LC057 & _LC059 & _LC060 & _LC064;
-- Node name is '|ADDRESS:18|LPM_ADD_SUB:135|addcore:adder|addcore:adder0|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC061', type is buried
_LC061 = LCELL( _LC051 $ _EQ019);
_EQ019 = _LC049 & _LC050 & _LC054 & _LC057 & _LC059 & _LC060 &
_LC064;
-- Node name is '|ADDRESS:18|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC058', type is buried
_LC058 = LCELL( _LC054 $ _EQ020);
_EQ020 = _LC049 & _LC059 & _LC060;
-- Node name is '|ADDRESS:18|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC056', type is buried
_LC056 = LCELL( _LC050 $ _EQ021);
_EQ021 = _LC049 & _LC054 & _LC059 & _LC060;
-- Node name is '|ADDRESS:18|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC055', type is buried
_LC055 = LCELL( _LC051 $ _EQ022);
_EQ022 = _LC049 & _LC050 & _LC054 & _LC059 & _LC060;
-- Node name is '|ADDRESS:18|:18' = '|ADDRESS:18|temp0'
-- Equation name is '_LC064', type is buried
_LC064 = TFFE( _EQ023, _LC020, VCC, VCC, VCC);
_EQ023 = _LC049 & _LC050 & _LC051 & _LC052 & _LC053 & _LC054 &
_LC057 & _LC059 & _LC060 & _LC064
# !s;
-- Node name is '|ADDRESS:18|:17' = '|ADDRESS:18|temp1'
-- Equation name is '_LC057', type is buried
_LC057 = TFFE( _EQ024, _LC020, VCC, VCC, VCC);
_EQ024 = _LC049 & _LC050 & _LC051 & _LC052 & _LC053 & _LC054 &
_LC057 & _LC059 & _LC060 & _LC064
# _LC064 & !s;
-- Node name is '|ADDRESS:18|:16' = '|ADDRESS:18|temp2'
-- Equation name is '_LC059', type is buried
_LC059 = TFFE( _EQ025, _LC020, VCC, VCC, VCC);
_EQ025 = _LC057 & _LC064
# s;
-- Node name is '|ADDRESS:18|:15' = '|ADDRESS:18|temp3'
-- Equation name is '_LC060', type is buried
_LC060 = TFFE( _EQ026, _LC020, VCC, VCC, VCC);
_EQ026 = _LC049 & _LC050 & _LC051 & _LC052 & _LC053 & _LC054 &
_LC057 & _LC059 & _LC060 & _LC064
# _LC057 & _LC059 & _LC064 & !s
# _LC059 & s;
-- Node name is '|ADDRESS:18|:14' = '|ADDRESS:18|temp4'
-- Equation name is '_LC049', type is buried
_LC049 = TFFE( _EQ027, _LC020, VCC, VCC, VCC);
_EQ027 = _LC049 & _LC050 & _LC051 & _LC052 & _LC053 & _LC054 &
_LC057 & _LC059 & _LC060 & _LC064
# _LC057 & _LC059 & _LC060 & _LC064 & !s
# _LC059 & _LC060 & s;
-- Node name is '|ADDRESS:18|:13' = '|ADDRESS:18|temp5'
-- Equation name is '_LC054', type is buried
_LC054 = DFFE( _EQ028 $ VCC, _LC020, VCC, VCC, VCC);
_EQ028 = _LC049 & _LC050 & _LC051 & _LC052 & _LC053 & _LC054 &
_LC057 & _LC059 & _LC060 & _LC064
# !_LC058 & s
# !_LC063 & !s;
-- Node name is '|ADDRESS:18|:12' = '|ADDRESS:18|temp6'
-- Equation name is '_LC050', type is buried
_LC050 = DFFE( _EQ029 $ VCC, _LC020, VCC, VCC, VCC);
_EQ029 = _LC049 & _LC050 & _LC051 & _LC052 & _LC053 & _LC054 &
_LC057 & _LC059 & _LC060 & _LC064
# !_LC056 & s
# !_LC062 & !s;
-- Node name is '|ADDRESS:18|:11' = '|ADDRESS:18|temp7'
-- Equation name is '_LC051', type is buried
_LC051 = DFFE( _EQ030 $ VCC, _LC020, VCC, VCC, VCC);
_EQ030 = _LC049 & _LC050 & _LC051 & _LC052 & _LC053 & _LC054 &
_LC057 & _LC059 & _LC060 & _LC064
# !_LC055 & s
# !_LC061 & !s;
-- Node name is '|ADDRESS:18|:10' = '|ADDRESS:18|temp8'
-- Equation name is '_LC052', type is buried
_LC052 = TFFE( _EQ031, _LC020, VCC, VCC, VCC);
_EQ031 = _LC049 & _LC050 & _LC051 & _LC052 & _LC053 & _LC054 &
_LC057 & _LC059 & _LC060 & _LC064
# _LC049 & _LC050 & _LC051 & _LC054 & _LC057 & _LC059 &
_LC060 & _LC064 & !s
# _LC049 & _LC050 & _LC051 & _LC054 & _LC059 & _LC060 & s;
-- Node name is '|ADDRESS:18|:9' = '|ADDRESS:18|temp9'
-- Equation name is '_LC053', type is buried
_LC053 = TFFE( _EQ032, _LC020, VCC, VCC, VCC);
_EQ032 = _LC049 & _LC050 & _LC051 & _LC052 & _LC053 & _LC054 &
_LC057 & _LC059 & _LC060 & _LC064
# _LC049 & _LC050 & _LC051 & _LC052 & _LC054 & _LC057 &
_LC059 & _LC060 & _LC064 & !s
# _LC049 & _LC050 & _LC051 & _LC052 & _LC054 & _LC059 &
_LC060 & s;
-- Node name is '|AD:2|:6' = '|AD:2|temp0'
-- Equation name is '_LC027', type is buried
_LC027 = TFFE( VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|AD:2|:5' = '|AD:2|temp1'
-- Equation name is '_LC039', type is buried
_LC039 = TFFE( _LC027, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|FREQUE4:4|:4' = '|FREQUE4:4|temp0'
-- Equation name is '_LC034', type is buried
_LC034 = TFFE( VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|FREQUE4:4|:3' = '|FREQUE4:4|temp1'
-- Equation name is '_LC020', type is buried
_LC020 = TFFE( _LC034, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|STORE:1|~2728~1'
-- Equation name is '_LC038', type is buried
-- synthesized logic cell
_LC038 = LCELL( _EQ033 $ GND);
_EQ033 = _LC050 & !_LC051 & !_LC052 & !_LC053 & !_LC054
# _LC050 & _LC051 & _LC052 & !_LC053
# !_LC050 & _LC052 & _LC053 & !_LC054
# !_LC049 & !_LC050 & _LC053 & !_LC054
# _LC051 & !_LC052 & _LC053;
-- Node name is '|STORE:1|~2917~1'
-- Equation name is '_LC041', type is buried
-- synthesized logic cell
_LC041 = LCELL( _EQ034 $ GND);
_EQ034 = _LC049 & !_LC050 & _LC051 & !_LC052 & !_LC053 & !_LC054
# _LC049 & !_LC050 & _LC051 & _LC053 & _LC054
# _LC049 & !_LC050 & !_LC053 & _LC054
# !_LC049 & _LC050 & !_LC051 & _LC053
# _LC051 & !_LC052 & _LC054;
-- Node name is '|STORE:1|~3106~1'
-- Equation name is '_LC042', type is buried
-- synthesized logic cell
_LC042 = LCELL( _EQ035 $ GND);
_EQ035 = _LC049 & !_LC050 & _LC051 & !_LC052 & _LC053 & _LC054
# _LC049 & !_LC050 & !_LC051 & !_LC052 & _LC053 & !_LC054
# !_LC049 & _LC050 & !_LC051 & !_LC052 & _LC053 & !_LC054
# !_LC049 & !_LC050 & !_LC051 & !_LC052 & _LC053 & _LC054
# _LC050 & !_LC051 & _LC052 & _LC053 & _LC054;
-- Node name is '|STORE:1|~3106~2'
-- Equation name is '_LC043', type is buried
-- synthesized logic cell
_LC043 = LCELL( _EQ036 $ GND);
_EQ036 = _LC049 & _LC050 & _LC052 & !_LC053 & _LC054
# !_LC049 & _LC050 & !_LC051 & !_LC053 & _LC054
# _LC049 & !_LC050 & !_LC052 & !_LC053 & !_LC054
# _LC049 & _LC050 & _LC051 & _LC052
# !_LC049 & !_LC050 & _LC051 & _LC054;
-- Node name is '|STORE:1|~3295~1'
-- Equation name is '_LC044', type is buried
-- synthesized logic cell
_LC044 = LCELL( _EQ037 $ GND);
_EQ037 = _LC050 & !_LC051 & !_LC052 & !_LC053 & _LC054
# _LC049 & !_LC051 & !_LC052 & !_LC053 & _LC054
# _LC049 & _LC051 & _LC053 & _LC054
# !_LC049 & _LC050 & _LC053 & _LC054
# !_LC050 & !_LC051 & _LC053 & _LC054;
-- Node name is '|STORE:1|~3484~1'
-- Equation name is '_LC045', type is buried
-- synthesized logic cell
_LC045 = LCELL( _EQ038 $ GND);
_EQ038 = !_LC049 & _LC050 & _LC051 & _LC052 & !_LC053
# !_LC049 & !_LC050 & !_LC051 & _LC053 & _LC054
# !_LC049 & _LC050 & !_LC051 & !_LC052 & !_LC054
# !_LC049 & !_LC050 & !_LC051 & _LC052 & !_LC054
# !_LC049 & !_LC050 & !_LC052 & !_LC053 & _LC054;
-- Node name is '|STORE:1|~3673~1'
-- Equation name is '_LC046', type is buried
-- synthesized logic cell
_LC046 = LCELL( _EQ039 $ GND);
_EQ039 = _LC049 & _LC050 & !_LC051 & !_LC052 & _LC054
# _LC049 & _LC050 & _LC051 & !_LC052 & !_LC054
# !_LC049 & !_LC050 & !_LC051 & _LC053 & !_LC054
# _LC051 & !_LC052 & _LC053 & _LC054
# _LC049 & _LC051 & !_LC052 & _LC053;
-- Node name is '|STORE:1|~3862~1'
-- Equation name is '_LC047', type is buried
-- synthesized logic cell
_LC047 = LCELL( _EQ040 $ GND);
_EQ040 = _LC049 & _LC050 & !_LC051 & _LC054
# !_LC049 & _LC051 & _LC053 & !_LC054
# _LC049 & !_LC050 & !_LC052 & !_LC053
# !_LC050 & !_LC051 & !_LC052 & _LC054
# !_LC049 & !_LC050 & _LC052 & !_LC054;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X006 occurs in LABs B, C
-- _X007 occurs in LABs B, C
-- _X008 occurs in LABs A, B
-- _X012 occurs in LABs A, B
Project Information e:\bfsk\fpgd.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,223K
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