fpgd.rpt

来自「基于bpsk的vhdl语言编程与性能仿真」· RPT 代码 · 共 910 行 · 第 1/3 页

LC51 -> * * * | * * * * | <-- |ADDRESS:18|temp7
LC50 -> * * * | * * * * | <-- |ADDRESS:18|temp6
LC54 -> * * * | * * * * | <-- |ADDRESS:18|temp5
LC49 -> * * * | * * * * | <-- |ADDRESS:18|temp4
LC38 -> - - * | * - - - | <-- |STORE:1|~2728~1
LC41 -> - * - | * - - - | <-- |STORE:1|~2917~1
LC44 -> * - - | * - - - | <-- |STORE:1|~3295~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                  e:\bfsk\fpgd.rpt
fpgd

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                 Logic cells placed in LAB 'B'
        +------- LC27 |AD:2|temp0
        | +----- LC19 d1
        | | +--- LC17 d2
        | | | +- LC20 |FREQUE4:4|temp1
        | | | | 
        | | | |   Other LABs fed by signals
        | | | |   that feed LAB 'B'
LC      | | | | | A B C D |     Logic cells that feed LAB 'B':

Pin
43   -> - - - - | - - - - | <-- clk
LC53 -> - * * - | * * * * | <-- |ADDRESS:18|temp9
LC52 -> - * * - | * * * * | <-- |ADDRESS:18|temp8
LC51 -> - * * - | * * * * | <-- |ADDRESS:18|temp7
LC50 -> - * * - | * * * * | <-- |ADDRESS:18|temp6
LC54 -> - * * - | * * * * | <-- |ADDRESS:18|temp5
LC49 -> - * * - | * * * * | <-- |ADDRESS:18|temp4
LC34 -> - - - * | - * - - | <-- |FREQUE4:4|temp0
LC45 -> - - * - | - * - - | <-- |STORE:1|~3484~1
LC46 -> - * - - | - * - - | <-- |STORE:1|~3673~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                  e:\bfsk\fpgd.rpt
fpgd

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

                                         Logic cells placed in LAB 'C'
        +------------------------------- LC36 ab
        | +----------------------------- LC39 |AD:2|temp1
        | | +--------------------------- LC48 cs
        | | | +------------------------- LC40 d0
        | | | | +----------------------- LC35 d4
        | | | | | +--------------------- LC33 d7
        | | | | | | +------------------- LC34 |FREQUE4:4|temp0
        | | | | | | | +----------------- LC38 |STORE:1|~2728~1
        | | | | | | | | +--------------- LC41 |STORE:1|~2917~1
        | | | | | | | | | +------------- LC42 |STORE:1|~3106~1
        | | | | | | | | | | +----------- LC43 |STORE:1|~3106~2
        | | | | | | | | | | | +--------- LC44 |STORE:1|~3295~1
        | | | | | | | | | | | | +------- LC45 |STORE:1|~3484~1
        | | | | | | | | | | | | | +----- LC46 |STORE:1|~3673~1
        | | | | | | | | | | | | | | +--- LC47 |STORE:1|~3862~1
        | | | | | | | | | | | | | | | +- LC37 wr
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'C'
LC      | | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'C':
LC39 -> * * * - - - - - - - - - - - - * | - - * - | <-- |AD:2|temp1
LC42 -> - - - - * - - - - - - - - - - - | - - * - | <-- |STORE:1|~3106~1
LC43 -> - - - - * - - - - - - - - - - - | - - * - | <-- |STORE:1|~3106~2
LC47 -> - - - * - - - - - - - - - - - - | - - * - | <-- |STORE:1|~3862~1

Pin
43   -> - - - - - - - - - - - - - - - - | - - - - | <-- clk
LC53 -> - - - * * * - * * * * * * * * - | * * * * | <-- |ADDRESS:18|temp9
LC52 -> - - - * * * - * * * * * * * * - | * * * * | <-- |ADDRESS:18|temp8
LC51 -> - - - * * * - * * * * * * * * - | * * * * | <-- |ADDRESS:18|temp7
LC50 -> - - - * * * - * * * * * * * * - | * * * * | <-- |ADDRESS:18|temp6
LC54 -> - - - * * * - * * * * * * * * - | * * * * | <-- |ADDRESS:18|temp5
LC49 -> - - - * * * - * * * * * * * * - | * * * * | <-- |ADDRESS:18|temp4
LC27 -> * * * - - - - - - - - - - - - * | - - * - | <-- |AD:2|temp0


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                  e:\bfsk\fpgd.rpt
fpgd

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                                         Logic cells placed in LAB 'D'
        +------------------------------- LC63 |ADDRESS:18|LPM_ADD_SUB:135|addcore:adder|addcore:adder0|result_node5
        | +----------------------------- LC62 |ADDRESS:18|LPM_ADD_SUB:135|addcore:adder|addcore:adder0|result_node6
        | | +--------------------------- LC61 |ADDRESS:18|LPM_ADD_SUB:135|addcore:adder|addcore:adder0|result_node7
        | | | +------------------------- LC58 |ADDRESS:18|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node5
        | | | | +----------------------- LC56 |ADDRESS:18|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node6
        | | | | | +--------------------- LC55 |ADDRESS:18|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node7
        | | | | | | +------------------- LC53 |ADDRESS:18|temp9
        | | | | | | | +----------------- LC52 |ADDRESS:18|temp8
        | | | | | | | | +--------------- LC51 |ADDRESS:18|temp7
        | | | | | | | | | +------------- LC50 |ADDRESS:18|temp6
        | | | | | | | | | | +----------- LC54 |ADDRESS:18|temp5
        | | | | | | | | | | | +--------- LC49 |ADDRESS:18|temp4
        | | | | | | | | | | | | +------- LC60 |ADDRESS:18|temp3
        | | | | | | | | | | | | | +----- LC59 |ADDRESS:18|temp2
        | | | | | | | | | | | | | | +--- LC57 |ADDRESS:18|temp1
        | | | | | | | | | | | | | | | +- LC64 |ADDRESS:18|temp0
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'D':
LC63 -> - - - - - - - - - - * - - - - - | - - - * | <-- |ADDRESS:18|LPM_ADD_SUB:135|addcore:adder|addcore:adder0|result_node5
LC62 -> - - - - - - - - - * - - - - - - | - - - * | <-- |ADDRESS:18|LPM_ADD_SUB:135|addcore:adder|addcore:adder0|result_node6
LC61 -> - - - - - - - - * - - - - - - - | - - - * | <-- |ADDRESS:18|LPM_ADD_SUB:135|addcore:adder|addcore:adder0|result_node7
LC58 -> - - - - - - - - - - * - - - - - | - - - * | <-- |ADDRESS:18|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node5
LC56 -> - - - - - - - - - * - - - - - - | - - - * | <-- |ADDRESS:18|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node6
LC55 -> - - - - - - - - * - - - - - - - | - - - * | <-- |ADDRESS:18|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node7
LC53 -> - - - - - - * * * * * * * - * * | * * * * | <-- |ADDRESS:18|temp9
LC52 -> - - - - - - * * * * * * * - * * | * * * * | <-- |ADDRESS:18|temp8
LC51 -> - - * - - * * * * * * * * - * * | * * * * | <-- |ADDRESS:18|temp7
LC50 -> - * * - * * * * * * * * * - * * | * * * * | <-- |ADDRESS:18|temp6
LC54 -> * * * * * * * * * * * * * - * * | * * * * | <-- |ADDRESS:18|temp5
LC49 -> * * * * * * * * * * * * * - * * | * * * * | <-- |ADDRESS:18|temp4
LC60 -> * * * * * * * * * * * * * - * * | - - - * | <-- |ADDRESS:18|temp3
LC59 -> * * * * * * * * * * * * * * * * | - - - * | <-- |ADDRESS:18|temp2
LC57 -> * * * - - - * * * * * * * * * * | - - - * | <-- |ADDRESS:18|temp1
LC64 -> * * * - - - * * * * * * * * * * | - - - * | <-- |ADDRESS:18|temp0

Pin
43   -> - - - - - - - - - - - - - - - - | - - - - | <-- clk
12   -> - - - - - - * * * * * * * * * * | - - - * | <-- s
LC20 -> - - - - - - * * * * * * * * * * | - - - * | <-- |FREQUE4:4|temp1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                  e:\bfsk\fpgd.rpt
fpgd

** EQUATIONS **

clk      : INPUT;
s        : INPUT;

-- Node name is 'ab' 
-- Equation name is 'ab', location is LC036, type is output.
 ab      = LCELL( _EQ001 $  _LC027);
  _EQ001 =  _LC027 & !_LC039;

-- Node name is 'cs' 
-- Equation name is 'cs', location is LC048, type is output.
 cs      = LCELL( _EQ002 $  _LC027);
  _EQ002 =  _LC027 & !_LC039;

-- Node name is 'd0' 
-- Equation name is 'd0', location is LC040, type is output.
 d0      = LCELL( _EQ003 $  _EQ004);
  _EQ003 = !_LC047 &  _LC050 & !_LC051 & !_LC052 &  _LC053 & !_LC054 &  _X001 & 
              _X002 &  _X003 &  _X004
         # !_LC047 & !_LC049 &  _LC050 & !_LC051 & !_LC052 & !_LC053 &  _X001 & 
              _X002 &  _X003 &  _X004
         # !_LC047 &  _LC049 &  _LC050 & !_LC053 &  _LC054 &  _X001 &  _X002 & 
              _X003 &  _X004
         # !_LC047 &  _LC049 &  _LC052 &  _LC053 & !_LC054 &  _X001 &  _X002 & 
              _X003 &  _X004;
  _X001  = EXP( _LC049 &  _LC050 &  _LC052);
  _X002  = EXP(!_LC049 &  _LC051 &  _LC052);
  _X003  = EXP(!_LC050 &  _LC051 & !_LC054);
  _X004  = EXP(!_LC049 & !_LC050 &  _LC053);
  _EQ004 = !_LC047 &  _X001 &  _X002 &  _X003 &  _X004;
  _X001  = EXP( _LC049 &  _LC050 &  _LC052);
  _X002  = EXP(!_LC049 &  _LC051 &  _LC052);
  _X003  = EXP(!_LC050 &  _LC051 & !_LC054);
  _X004  = EXP(!_LC049 & !_LC050 &  _LC053);

-- Node name is 'd1' 
-- Equation name is 'd1', location is LC019, type is output.
 d1      = LCELL( _EQ005 $  _EQ006);
  _EQ005 =  _LC049 &  _LC051 &  _LC052 & !_LC053 & !_LC054
         #  _LC050 &  _LC051 & !_LC053 &  _X005
         #  _LC050 & !_LC053 & !_LC054 &  _X005;
  _X005  = EXP( _LC049 & !_LC052);
  _EQ006 = !_LC046 &  _X006 &  _X007 &  _X008 &  _X009 &  _X010 &  _X011 & 
              _X012 &  _X013;
  _X006  = EXP( _LC049 &  _LC050 & !_LC051 &  _LC053 &  _LC054);
  _X007  = EXP( _LC049 & !_LC050 & !_LC051 & !_LC052 & !_LC053);
  _X008  = EXP(!_LC050 & !_LC051 &  _LC052 &  _LC053);
  _X009  = EXP(!_LC050 & !_LC051 &  _LC052 &  _LC054);
  _X010  = EXP(!_LC049 & !_LC051 &  _LC052 &  _LC054);
  _X011  = EXP(!_LC049 & !_LC051 &  _LC052 &  _LC053);
  _X012  = EXP(!_LC049 & !_LC050 &  _LC052 &  _LC053);
  _X013  = EXP(!_LC050 & !_LC052 & !_LC053 &  _LC054);

-- Node name is 'd2' 
-- Equation name is 'd2', location is LC017, type is output.
 d2      = LCELL( _EQ007 $  _EQ008);
  _EQ007 = !_LC045 &  _LC049 & !_LC051 &  _LC052 & !_LC053 &  _LC054 &  _X008 & 
              _X014 &  _X015 &  _X016 &  _X017 &  _X018
         # !_LC045 &  _LC049 &  _LC050 &  _LC051 & !_LC052 & !_LC054 &  _X008 & 
              _X014 &  _X015 &  _X016 &  _X017 &  _X018
         # !_LC045 & !_LC049 &  _LC050 &  _LC052 & !_LC053 &  _LC054 &  _X008 & 
              _X014 &  _X015 &  _X016 &  _X017 &  _X018
         # !_LC045 &  _LC050 & !_LC051 & !_LC052 &  _LC053 &  _LC054 &  _X008 & 
              _X014 &  _X015 &  _X016 &  _X017 &  _X018;
  _X008  = EXP(!_LC050 & !_LC051 &  _LC052 &  _LC053);
  _X014  = EXP( _LC049 & !_LC050 &  _LC051 & !_LC053);
  _X015  = EXP( _LC049 &  _LC050 &  _LC051 &  _LC053);
  _X016  = EXP(!_LC050 &  _LC052 &  _LC053 &  _LC054);
  _X017  = EXP( _LC049 &  _LC050 & !_LC051 & !_LC053);
  _X018  = EXP(!_LC050 &  _LC051 & !_LC053 & !_LC054);
  _EQ008 = !_LC045 &  _X008 &  _X014 &  _X015 &  _X016 &  _X017 &  _X018;
  _X008  = EXP(!_LC050 & !_LC051 &  _LC052 &  _LC053);
  _X014  = EXP( _LC049 & !_LC050 &  _LC051 & !_LC053);
  _X015  = EXP( _LC049 &  _LC050 &  _LC051 &  _LC053);
  _X016  = EXP(!_LC050 &  _LC052 &  _LC053 &  _LC054);
  _X017  = EXP( _LC049 &  _LC050 & !_LC051 & !_LC053);
  _X018  = EXP(!_LC050 &  _LC051 & !_LC053 & !_LC054);

-- Node name is 'd3' 
-- Equation name is 'd3', location is LC005, type is output.
 d3      = LCELL( _EQ009 $  _EQ010);
  _EQ009 = !_LC044 & !_LC049 & !_LC050 &  _LC051 &  _LC052 & !_LC053 & 
              _LC054 &  _X008 &  _X019 &  _X020 &  _X021 &  _X022
         # !_LC044 &  _LC049 &  _LC051 &  _LC052 & !_LC053 & !_LC054 &  _X008 & 
              _X019 &  _X020 &  _X021 &  _X022
         # !_LC044 &  _LC049 &  _LC050 & !_LC051 &  _LC052 & !_LC053 &  _X008 & 
              _X019 &  _X020 &  _X021 &  _X022
         # !_LC044 & !_LC049 & !_LC050 &  _LC052 &  _LC053 & !_LC054 &  _X008 & 
              _X019 &  _X020 &  _X021 &  _X022;
  _X008  = EXP(!_LC050 & !_LC051 &  _LC052 &  _LC053);
  _X019  = EXP(!_LC049 &  _LC050 & !_LC053 & !_LC054);
  _X020  = EXP( _LC050 &  _LC052 & !_LC053 & !_LC054);
  _X021  = EXP( _LC049 & !_LC050 &  _LC051 & !_LC052);
  _X022  = EXP(!_LC049 & !_LC051 &  _LC052 & !_LC054);
  _EQ010 = !_LC044 &  _X008 &  _X019 &  _X020 &  _X021 &  _X022;
  _X008  = EXP(!_LC050 & !_LC051 &  _LC052 &  _LC053);
  _X019  = EXP(!_LC049 &  _LC050 & !_LC053 & !_LC054);
  _X020  = EXP( _LC050 &  _LC052 & !_LC053 & !_LC054);
  _X021  = EXP( _LC049 & !_LC050 &  _LC051 & !_LC052);
  _X022  = EXP(!_LC049 & !_LC051 &  _LC052 & !_LC054);

-- Node name is 'd4' 
-- Equation name is 'd4', location is LC035, type is output.
 d4      = LCELL( _EQ011 $  _LC053);
  _EQ011 = !_LC042 & !_LC043 &  _X006 &  _X007;
  _X006  = EXP( _LC049 &  _LC050 & !_LC051 &  _LC053 &  _LC054);
  _X007  = EXP( _LC049 & !_LC050 & !_LC051 & !_LC052 & !_LC053);

-- Node name is 'd5' 
-- Equation name is 'd5', location is LC004, type is output.
 d5      = LCELL( _EQ012 $ !_LC053);
  _EQ012 = !_LC041 &  _X023 &  _X024 &  _X025;
  _X023  = EXP(!_LC049 & !_LC051 & !_LC054);
  _X024  = EXP( _LC050 & !_LC054);
  _X025  = EXP(!_LC051 &  _LC052);

-- Node name is 'd6' 
-- Equation name is 'd6', location is LC003, type is output.
 d6      = LCELL( _EQ013 $  _EQ014);
  _EQ013 = !_LC038 &  _LC049 &  _LC050 & !_LC052 &  _LC053 &  _LC054 &  _X012 & 
              _X026
         # !_LC038 &  _LC049 &  _LC051 &  _LC052 & !_LC053 &  _LC054 &  _X012 & 
              _X026
         # !_LC038 & !_LC050 & !_LC051 & !_LC052 & !_LC053 &  _LC054 &  _X012 & 
              _X026
         # !_LC038 &  _LC049 & !_LC050 & !_LC051 & !_LC052 & !_LC053 &  _X012 & 
              _X026;
  _X012  = EXP(!_LC049 & !_LC050 &  _LC052 &  _LC053);
  _X026  = EXP(!_LC051 &  _LC052 &  _LC053);
  _EQ014 = !_LC038 &  _X012 &  _X026;
  _X012  = EXP(!_LC049 & !_LC050 &  _LC052 &  _LC053);
  _X026  = EXP(!_LC051 &  _LC052 &  _LC053);

-- Node name is 'd7' 
-- Equation name is 'd7', location is LC033, type is output.
 d7      = LCELL( _EQ015 $ !_LC053);
  _EQ015 = !_LC049 & !_LC050 & !_LC051 & !_LC052 &  _LC053 & !_LC054
         # !_LC049 & !_LC050 & !_LC051 & !_LC053 & !_LC054;

-- Node name is 'wr' 
-- Equation name is 'wr', location is LC037, type is output.
 wr      = LCELL( _EQ016 $  VCC);
  _EQ016 =  _LC027 & !_LC039;

-- Node name is '|ADDRESS:18|LPM_ADD_SUB:135|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC063', type is buried 
_LC063   = LCELL( _LC054 $  _EQ017);
  _EQ017 =  _LC049 &  _LC057 &  _LC059 &  _LC060 &  _LC064;

-- Node name is '|ADDRESS:18|LPM_ADD_SUB:135|addcore:adder|addcore:adder0|result_node6' from file "addcore.tdf" line 164, column 16