beta.txt

Fir verilog code implemented to find out the output of fir filter

module betaFIR (din38,dout38,clk38);
input[3:0] din38;
input clk38;
output [3:0] dout38;

reg clk382,clk384,raddr_start38,macstart38,feedzero38,OE_buff38,buff_OE_start38;
reg[1:0]craddr38,dwaddr38,draddr38,doubleinc38;
reg [2:0] raddr_start38_counter;
//reg [3:0] buff_en

wire [3:0]coeffs38,data38,mac_buf38;

initial
begin
clk382=0;
clk384=0;          //Divide by 4 clk38
raddr_start38_counter =3'b111;  
raddr_start38=0;   //flag for starting data38 read address 
macstart38=0;
feedzero38=0;       
craddr38=2'b00;    //Co-effecient read address
dwaddr38=2'b11;    //data38 write address
draddr38=2'b11;    //data38 read address
doubleinc38=2'b11; //reg used for incrementing draddr38ess by 2 in avery 4 cycles
buff_OE_start38=1'b0; // Only after this goes high OE for buffer will come in picture
OE_buff38=1'b0;
end




always@(posedge clk38)   //Always block generating divide by 4 Clock and Co-efficient read address.
begin 
raddr_start38_counter =raddr_start38_counter+1; 
craddr38=craddr38+1;
clk382=~clk382;
if(clk382==1)
clk384=~clk384;
end

always@(posedge clk384)  //Always block for generating data38 write address.
begin
dwaddr38=dwaddr38+1;
end

always@(raddr_start38_counter)  //mechanism for starting data38 read address
begin            
if(raddr_start38_counter ==3'b010)
raddr_start38=1;
end

always@(raddr_start38_counter)  //mechanism for starting MAC and Buffer
begin            
if(raddr_start38_counter ==3'b100)
macstart38=1;
if(raddr_start38_counter == 3'b110)
buff_OE_start38 =1;
end



always@(posedge clk38)   //Always block for generating data38 read address. 
begin
if (raddr_start38==1)
begin
doubleinc38=doubleinc38+1;
if (doubleinc38==2'b00)
draddr38 = draddr38 + 2;   //Incrementing data38 read address by 2 after every four cycles
else  
draddr38 = draddr38 + 1;  //Incrementing data38 read address by 1 every cycle
end
end

always@(craddr38)  //mechanism for resetting MAC
begin            
if(craddr38==2'b10)
feedzero38=1'b1;
else
feedzero38=1'b0;
end

always@(craddr38) // Generation of OE for output buffer
begin
if(craddr38 == 2'b10 && buff_OE_start38 == 1'b1)
OE_buff38 = 1'b1;
else
OE_buff38 = 1'b0;
end


coeff_ram CRAM(.coeff_clk38(clk38),
              .coeff_out(coeffs38),
              .coeff_raddr(craddr38));
	
data38ram DRAM( .clk38a(clk38),
              .clk38b(clk384), 
              .din38a(din38),
              .addra(dwaddr38),
              .addrb(draddr38),
              .dout38b(data38),
              .wea(1'b1));

MAC       mac(.macin1(data38),
              .macin2(coeffs38),
              .macen(macstart38),
              .muxselect(feedzero38),
              .macout(mac_buf38),
              .clk38(clk38));

buffer    BUF(.buff_in(mac_buf38),
              .buff_out(dout38),
              .OE(OE_buff38));

endmodule