jsq.tan.rpt

TI公司的TLC5510的用VHDL写的控制器及其仿真

; Minimum Slack ; Required th ; Actual th ; From ; To        ; To Clock ;
+---------------+-------------+-----------+------+-----------+----------+
; N/A           ; None        ; -0.762 ns ; CLR  ; OUT1~reg0 ; CLK      ;
; N/A           ; None        ; -5.519 ns ; EN   ; OUT1~reg0 ; CLK      ;
; N/A           ; None        ; -6.477 ns ; EN   ; DATA[0]   ; CLK      ;
; N/A           ; None        ; -6.477 ns ; EN   ; DATA[13]  ; CLK      ;
; N/A           ; None        ; -6.477 ns ; EN   ; DATA[15]  ; CLK      ;
; N/A           ; None        ; -6.477 ns ; EN   ; DATA[14]  ; CLK      ;
; N/A           ; None        ; -6.477 ns ; EN   ; DATA[10]  ; CLK      ;
; N/A           ; None        ; -6.477 ns ; EN   ; DATA[11]  ; CLK      ;
; N/A           ; None        ; -6.477 ns ; EN   ; DATA[9]   ; CLK      ;
; N/A           ; None        ; -6.477 ns ; EN   ; DATA[12]  ; CLK      ;
; N/A           ; None        ; -6.477 ns ; EN   ; DATA[1]   ; CLK      ;
; N/A           ; None        ; -6.477 ns ; EN   ; DATA[2]   ; CLK      ;
; N/A           ; None        ; -6.477 ns ; EN   ; DATA[4]   ; CLK      ;
; N/A           ; None        ; -6.477 ns ; EN   ; DATA[3]   ; CLK      ;
; N/A           ; None        ; -6.477 ns ; EN   ; DATA[5]   ; CLK      ;
; N/A           ; None        ; -6.477 ns ; EN   ; DATA[7]   ; CLK      ;
; N/A           ; None        ; -6.477 ns ; EN   ; DATA[8]   ; CLK      ;
; N/A           ; None        ; -6.477 ns ; EN   ; DATA[6]   ; CLK      ;
+---------------+-------------+-----------+------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Thu May 07 17:02:06 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off jsq -c jsq --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 182.85 MHz between source register "DATA[10]" and destination register "DATA[0]" (period= 5.469 ns)
    Info: + Longest register to register delay is 5.205 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y11_N21; Fanout = 4; REG Node = 'DATA[10]'
        Info: 2: + IC(1.137 ns) + CELL(0.534 ns) = 1.671 ns; Loc. = LCCOMB_X13_Y11_N16; Fanout = 1; COMB Node = 'OUT1~294'
        Info: 3: + IC(0.395 ns) + CELL(0.615 ns) = 2.681 ns; Loc. = LCCOMB_X13_Y11_N6; Fanout = 2; COMB Node = 'OUT1~295'
        Info: 4: + IC(0.362 ns) + CELL(0.206 ns) = 3.249 ns; Loc. = LCCOMB_X13_Y11_N0; Fanout = 2; COMB Node = 'LessThan0~151'
        Info: 5: + IC(0.365 ns) + CELL(0.206 ns) = 3.820 ns; Loc. = LCCOMB_X13_Y11_N14; Fanout = 16; COMB Node = 'DATA[0]~495'
        Info: 6: + IC(0.530 ns) + CELL(0.855 ns) = 5.205 ns; Loc. = LCFF_X14_Y11_N1; Fanout = 5; REG Node = 'DATA[0]'
        Info: Total cell delay = 2.416 ns ( 46.42 % )
        Info: Total interconnect delay = 2.789 ns ( 53.58 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 2.788 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'CLK'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 17; COMB Node = 'CLK~clkctrl'
            Info: 3: + IC(0.893 ns) + CELL(0.666 ns) = 2.788 ns; Loc. = LCFF_X14_Y11_N1; Fanout = 5; REG Node = 'DATA[0]'
            Info: Total cell delay = 1.756 ns ( 62.98 % )
            Info: Total interconnect delay = 1.032 ns ( 37.02 % )
        Info: - Longest clock path from clock "CLK" to source register is 2.788 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'CLK'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 17; COMB Node = 'CLK~clkctrl'
            Info: 3: + IC(0.893 ns) + CELL(0.666 ns) = 2.788 ns; Loc. = LCFF_X14_Y11_N21; Fanout = 4; REG Node = 'DATA[10]'
            Info: Total cell delay = 1.756 ns ( 62.98 % )
            Info: Total interconnect delay = 1.032 ns ( 37.02 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "DATA[0]" (data pin = "EN", clock pin = "CLK") is 6.743 ns
    Info: + Longest pin to register delay is 9.571 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_126; Fanout = 2; PIN Node = 'EN'
        Info: 2: + IC(6.628 ns) + CELL(0.624 ns) = 8.186 ns; Loc. = LCCOMB_X13_Y11_N14; Fanout = 16; COMB Node = 'DATA[0]~495'
        Info: 3: + IC(0.530 ns) + CELL(0.855 ns) = 9.571 ns; Loc. = LCFF_X14_Y11_N1; Fanout = 5; REG Node = 'DATA[0]'
        Info: Total cell delay = 2.413 ns ( 25.21 % )
        Info: Total interconnect delay = 7.158 ns ( 74.79 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.788 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 17; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(0.893 ns) + CELL(0.666 ns) = 2.788 ns; Loc. = LCFF_X14_Y11_N1; Fanout = 5; REG Node = 'DATA[0]'
        Info: Total cell delay = 1.756 ns ( 62.98 % )
        Info: Total interconnect delay = 1.032 ns ( 37.02 % )
Info: tco from clock "CLK" to destination pin "INDATA[7]" through register "DATA[7]" is 9.257 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.788 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 17; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(0.893 ns) + CELL(0.666 ns) = 2.788 ns; Loc. = LCFF_X14_Y11_N15; Fanout = 4; REG Node = 'DATA[7]'
        Info: Total cell delay = 1.756 ns ( 62.98 % )
        Info: Total interconnect delay = 1.032 ns ( 37.02 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 6.165 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y11_N15; Fanout = 4; REG Node = 'DATA[7]'
        Info: 2: + IC(2.949 ns) + CELL(3.216 ns) = 6.165 ns; Loc. = PIN_118; Fanout = 0; PIN Node = 'INDATA[7]'
        Info: Total cell delay = 3.216 ns ( 52.17 % )
        Info: Total interconnect delay = 2.949 ns ( 47.83 % )
Info: th for register "OUT1~reg0" (data pin = "CLR", clock pin = "CLK") is -0.762 ns
    Info: + Longest clock path from clock "CLK" to destination register is 2.788 ns
        Info: 1: