jishu60.map.rpt

verilog实例

+----------------------+--------------------------------------+
; Logic cells          ; 24                                   ;
; Total registers      ; 7                                    ;
; I/O pins             ; 20                                   ;
; Maximum fan-out node ; jishi:u1|lpm_counter:q_rtl_1|dffs[0] ;
; Maximum fan-out      ; 14                                   ;
; Total fan-out        ; 123                                  ;
; Average fan-out      ; 2.80                                 ;
+----------------------+--------------------------------------+


+------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                      ;
+-----------------------------+------------+------+----------------------------------------+
; Compilation Hierarchy Node  ; Macrocells ; Pins ; Full Hierarchy Name                    ;
+-----------------------------+------------+------+----------------------------------------+
; |jishu60                    ; 24         ; 20   ; |jishu60                               ;
;    |Dec7s:u3|               ; 7          ; 0    ; |jishu60|Dec7s:u3                      ;
;    |Dec7s:u4|               ; 7          ; 0    ; |jishu60|Dec7s:u4                      ;
;    |block1:u2|              ; 4          ; 0    ; |jishu60|block1:u2                     ;
;       |lpm_counter:q_rtl_0| ; 3          ; 0    ; |jishu60|block1:u2|lpm_counter:q_rtl_0 ;
;    |jishi:u1|               ; 4          ; 0    ; |jishu60|jishi:u1                      ;
;       |lpm_counter:q_rtl_1| ; 4          ; 0    ; |jishu60|jishi:u1|lpm_counter:q_rtl_1  ;
+-----------------------------+------------+------+----------------------------------------+


+--------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: block1:u2|lpm_counter:q_rtl_0 ;
+------------------------+-------------------+-----------------------------------+
; Parameter Name         ; Value             ; Type                              ;
+------------------------+-------------------+-----------------------------------+
; AUTO_CARRY_CHAINS      ; ON                ; AUTO_CARRY                        ;
; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY                      ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE                      ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE                    ;
; LPM_WIDTH              ; 4                 ; Untyped                           ;
; LPM_DIRECTION          ; UP                ; Untyped                           ;
; LPM_MODULUS            ; 0                 ; Untyped                           ;
; LPM_AVALUE             ; UNUSED            ; Untyped                           ;
; LPM_SVALUE             ; UNUSED            ; Untyped                           ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                           ;
; DEVICE_FAMILY          ; MAX7000S          ; Untyped                           ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                           ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH                ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK                ;
; CARRY_CNT_EN           ; SMART             ; Untyped                           ;
; LABWIDE_SCLR           ; ON                ; Untyped                           ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                           ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                           ;
+------------------------+-------------------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: jishi:u1|lpm_counter:q_rtl_1 ;
+------------------------+-------------------+----------------------------------+
; Parameter Name         ; Value             ; Type                             ;
+------------------------+-------------------+----------------------------------+
; AUTO_CARRY_CHAINS      ; ON                ; AUTO_CARRY                       ;
; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY                     ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE                     ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE                   ;
; LPM_WIDTH              ; 4                 ; Untyped                          ;
; LPM_DIRECTION          ; UP                ; Untyped                          ;
; LPM_MODULUS            ; 0                 ; Untyped                          ;
; LPM_AVALUE             ; UNUSED            ; Untyped                          ;
; LPM_SVALUE             ; UNUSED            ; Untyped                          ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                          ;
; DEVICE_FAMILY          ; MAX7000S          ; Untyped                          ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                          ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH               ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK               ;
; CARRY_CNT_EN           ; SMART             ; Untyped                          ;
; LABWIDE_SCLR           ; ON                ; Untyped                          ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                          ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                          ;
+------------------------+-------------------+----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed May 06 13:18:34 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jishu60 -c jishu60
Info: Found 1 design units, including 1 entities, in source file jishu60.v
    Info: Found entity 1: jishu60
Info: Elaborating entity "jishu60" for the top level hierarchy
Warning: Using design file jishi.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: jishi
Info: Elaborating entity "jishi" for hierarchy "jishi:u1"
Warning (10230): Verilog HDL assignment warning at jishi.v(10): truncated value with size 32 to match size of target (4)
Warning: Using design file block1.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: block1
Info: Elaborating entity "block1" for hierarchy "block1:u2"
Warning (10230): Verilog HDL assignment warning at block1.v(10): truncated value with size 32 to match size of target (4)
Warning: Using design file Dec7s.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: Dec7s
Info: Elaborating entity "Dec7s" for hierarchy "Dec7s:u3"
Info: Inferred 2 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "block1:u2|q[0]~4"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "jishi:u1|q[0]~4"
Info: Found 1 design units, including 1 entities, in source file d:/programe files/quatus 60/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborated megafunction instantiation "block1:u2|lpm_counter:q_rtl_0"
Warning: Reduced register "block1:u2|lpm_counter:q_rtl_0|dffs[3]" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "q[7]" stuck at GND
    Warning: Pin "q[15]" stuck at GND
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clk" to global clock signal
Info: Implemented 44 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 17 output pins
    Info: Implemented 24 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings
    Info: Processing ended: Wed May 06 13:18:35 2009
    Info: Elapsed time: 00:00:02