jishu60.tan.qmsg

verilog实例

{ "Info" "ITDB_TH_RESULT" "jishi:u1\|lpm_counter:q_rtl_1\|dffs\[0\] ena clk -2.000 ns register " "Info: th for register \"jishi:u1\|lpm_counter:q_rtl_1\|dffs\[0\]\" (data pin = \"ena\", clock pin = \"clk\") is -2.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.500 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_83 7 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 7; CLK Node = 'clk'" {  } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jishu60.v" "" { Text "E:/作业/大二第二学期/verilog/新建文件夹 (2)/中/jishu60.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns jishi:u1\|lpm_counter:q_rtl_1\|dffs\[0\] 2 REG LC2 35 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2; Fanout = 35; REG Node = 'jishi:u1\|lpm_counter:q_rtl_1\|dffs\[0\]'" {  } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "0.000 ns" { clk jishi:u1|lpm_counter:q_rtl_1|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/programe files/quatus 60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { clk jishi:u1|lpm_counter:q_rtl_1|dffs[0] } "NODE_NAME" } } { "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "1.500 ns" { clk clk~out jishi:u1|lpm_counter:q_rtl_1|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/programe files/quatus 60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns ena 1 PIN PIN_52 9 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_52; Fanout = 9; PIN Node = 'ena'" {  } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "" { ena } "NODE_NAME" } } { "jishu60.v" "" { Text "E:/作业/大二第二学期/verilog/新建文件夹 (2)/中/jishu60.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns jishi:u1\|lpm_counter:q_rtl_1\|dffs\[0\] 2 REG LC2 35 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC2; Fanout = 35; REG Node = 'jishi:u1\|lpm_counter:q_rtl_1\|dffs\[0\]'" {  } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "6.000 ns" { ena jishi:u1|lpm_counter:q_rtl_1|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/programe files/quatus 60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 84.62 % ) " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 15.38 % ) " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "6.500 ns" { ena jishi:u1|lpm_counter:q_rtl_1|dffs[0] } "NODE_NAME" } } { "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "6.500 ns" { ena ena~out jishi:u1|lpm_counter:q_rtl_1|dffs[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { clk jishi:u1|lpm_counter:q_rtl_1|dffs[0] } "NODE_NAME" } } { "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "1.500 ns" { clk clk~out jishi:u1|lpm_counter:q_rtl_1|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/programe files/quatus 60/win/TimingClosureFloorplan.fld" "" "6.500 ns" { ena jishi:u1|lpm_counter:q_rtl_1|dffs[0] } "NODE_NAME" } } { "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/programe files/quatus 60/win/Technology_Viewer.qrui" "6.500 ns" { ena ena~out jishi:u1|lpm_counter:q_rtl_1|dffs[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 06 13:18:40 2009 " "Info: Processing ended: Wed May 06 13:18:40 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}