📄 jishu60.fit.rpt
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+----------------------------+------------------+
; Output enables ; 0 / 6 ( 0 % ) ;
; PIA buffers ; 13 / 288 ( 5 % ) ;
; PIAs ; 13 / 288 ( 5 % ) ;
+----------------------------+------------------+
+----------------------------------------------------------------------------+
; LAB External Interconnect ;
+----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 1.63) ; Number of LABs (Total = 2) ;
+----------------------------------------------+-----------------------------+
; 0 ; 6 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 1 ;
+----------------------------------------------+-----------------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 3.00) ; Number of LABs (Total = 3) ;
+----------------------------------------+-----------------------------+
; 0 ; 5 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 1 ;
+----------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC2 ; clk, jishi:u1|lpm_counter:q_rtl_1|dffs[0], jishi:u1|lpm_counter:q_rtl_1|dffs[3], ena, jishi:u1|lpm_counter:q_rtl_1|dffs[1], jishi:u1|lpm_counter:q_rtl_1|dffs[2], clr ; jishi:u1|lpm_counter:q_rtl_1|dffs[0], block1:u2|lpm_counter:q_rtl_0|dffs[1], jishi:u1|lpm_counter:q_rtl_1|dffs[1], block1:u2|lpm_counter:q_rtl_0|dffs[2], jishi:u1|lpm_counter:q_rtl_1|dffs[2], jishi:u1|lpm_counter:q_rtl_1|dffs[3], block1:u2|lpm_counter:q_rtl_0|dffs[0], Dec7s:u3|WideOr1~88, Dec7s:u3|WideOr0~118, Dec7s:u3|WideOr2~164, Dec7s:u3|WideOr6~226, Dec7s:u3|WideOr3~157, Dec7s:u3|WideOr5~238, Dec7s:u3|WideOr4~127 ;
; A ; LC9 ; clk, jishi:u1|lpm_counter:q_rtl_1|dffs[3], jishi:u1|lpm_counter:q_rtl_1|dffs[0], jishi:u1|lpm_counter:q_rtl_1|dffs[1], jishi:u1|lpm_counter:q_rtl_1|dffs[2], block1:u2|lpm_counter:q_rtl_0|dffs[2], block1:u2|lpm_counter:q_rtl_0|dffs[0], block1:u2|lpm_counter:q_rtl_0|dffs[1], clr ; block1:u2|lpm_counter:q_rtl_0|dffs[1], block1:u2|lpm_counter:q_rtl_0|dffs[2], block1:u2|lpm_counter:q_rtl_0|dffs[0], block1:u2|cout~36, Dec7s:u4|WideOr4~91, Dec7s:u4|WideOr2~104, Dec7s:u4|WideOr6~185, Dec7s:u4|WideOr5~144, Dec7s:u4|WideOr3~116, Dec7s:u4|WideOr1~73, Dec7s:u4|WideOr0~87 ;
; A ; LC1 ; clk, jishi:u1|lpm_counter:q_rtl_1|dffs[3], ena, jishi:u1|lpm_counter:q_rtl_1|dffs[1], jishi:u1|lpm_counter:q_rtl_1|dffs[0], clr ; jishi:u1|lpm_counter:q_rtl_1|dffs[0], block1:u2|lpm_counter:q_rtl_0|dffs[1], jishi:u1|lpm_counter:q_rtl_1|dffs[1], block1:u2|lpm_counter:q_rtl_0|dffs[2], jishi:u1|lpm_counter:q_rtl_1|dffs[2], jishi:u1|lpm_counter:q_rtl_1|dffs[3], block1:u2|lpm_counter:q_rtl_0|dffs[0], Dec7s:u3|WideOr1~88, Dec7s:u3|WideOr0~118, Dec7s:u3|WideOr2~164, Dec7s:u3|WideOr6~226, Dec7s:u3|WideOr3~157, Dec7s:u3|WideOr5~238, Dec7s:u3|WideOr4~127 ;
; A ; LC12 ; clk, jishi:u1|lpm_counter:q_rtl_1|dffs[3], jishi:u1|lpm_counter:q_rtl_1|dffs[0], jishi:u1|lpm_counter:q_rtl_1|dffs[1], jishi:u1|lpm_counter:q_rtl_1|dffs[2], block1:u2|lpm_counter:q_rtl_0|dffs[0], block1:u2|lpm_counter:q_rtl_0|dffs[1], block1:u2|lpm_counter:q_rtl_0|dffs[2], clr ; block1:u2|lpm_counter:q_rtl_0|dffs[1], block1:u2|lpm_counter:q_rtl_0|dffs[2], block1:u2|lpm_counter:q_rtl_0|dffs[0], block1:u2|cout~36, Dec7s:u4|WideOr4~91, Dec7s:u4|WideOr2~104, Dec7s:u4|WideOr6~185, Dec7s:u4|WideOr5~144, Dec7s:u4|WideOr3~116, Dec7s:u4|WideOr1~73, Dec7s:u4|WideOr0~87 ;
; A ; LC7 ; clk, jishi:u1|lpm_counter:q_rtl_1|dffs[3], ena, jishi:u1|lpm_counter:q_rtl_1|dffs[2], jishi:u1|lpm_counter:q_rtl_1|dffs[1], jishi:u1|lpm_counter:q_rtl_1|dffs[0], clr ; jishi:u1|lpm_counter:q_rtl_1|dffs[0], block1:u2|lpm_counter:q_rtl_0|dffs[1], block1:u2|lpm_counter:q_rtl_0|dffs[2], jishi:u1|lpm_counter:q_rtl_1|dffs[2], jishi:u1|lpm_counter:q_rtl_1|dffs[3], block1:u2|lpm_counter:q_rtl_0|dffs[0], Dec7s:u3|WideOr1~88, Dec7s:u3|WideOr0~118, Dec7s:u3|WideOr2~164, Dec7s:u3|WideOr6~226, Dec7s:u3|WideOr3~157, Dec7s:u3|WideOr5~238, Dec7s:u3|WideOr4~127 ;
; A ; LC4 ; clk, jishi:u1|lpm_counter:q_rtl_1|dffs[1], jishi:u1|lpm_counter:q_rtl_1|dffs[2], jishi:u1|lpm_counter:q_rtl_1|dffs[0], ena, jishi:u1|lpm_counter:q_rtl_1|dffs[3], clr ; jishi:u1|lpm_counter:q_rtl_1|dffs[0], block1:u2|lpm_counter:q_rtl_0|dffs[1], jishi:u1|lpm_counter:q_rtl_1|dffs[1], block1:u2|lpm_counter:q_rtl_0|dffs[2], jishi:u1|lpm_counter:q_rtl_1|dffs[2], jishi:u1|lpm_counter:q_rtl_1|dffs[3], block1:u2|lpm_counter:q_rtl_0|dffs[0], Dec7s:u3|WideOr1~88, Dec7s:u3|WideOr0~118, Dec7s:u3|WideOr2~164, Dec7s:u3|WideOr6~226, Dec7s:u3|WideOr3~157, Dec7s:u3|WideOr5~238, Dec7s:u3|WideOr4~127 ;
; A ; LC10 ; clk, block1:u2|lpm_counter:q_rtl_0|dffs[0], jishi:u1|lpm_counter:q_rtl_1|dffs[3], jishi:u1|lpm_counter:q_rtl_1|dffs[0], jishi:u1|lpm_counter:q_rtl_1|dffs[1], jishi:u1|lpm_counter:q_rtl_1|dffs[2], block1:u2|lpm_counter:q_rtl_0|dffs[2], block1:u2|lpm_counter:q_rtl_0|dffs[1], clr ; block1:u2|lpm_counter:q_rtl_0|dffs[1], block1:u2|lpm_counter:q_rtl_0|dffs[2], block1:u2|lpm_counter:q_rtl_0|dffs[0], block1:u2|cout~36, Dec7s:u4|WideOr4~91, Dec7s:u4|WideOr2~104, Dec7s:u4|WideOr6~185, Dec7s:u4|WideOr5~144, Dec7s:u4|WideOr3~116, Dec7s:u4|WideOr1~73, Dec7s:u4|WideOr0~87 ;
; A ; LC5 ; block1:u2|lpm_counter:q_rtl_0|dffs[0], block1:u2|lpm_counter:q_rtl_0|dffs[2], block1:u2|lpm_counter:q_rtl_0|dffs[1] ; cout ;
; A ; LC6 ; block1:u2|lpm_counter:q_rtl_0|dffs[0], block1:u2|lpm_counter:q_rtl_0|dffs[2], block1:u2|lpm_counter:q_rtl_0|dffs[1] ; q[10] ;
; A ; LC8 ; block1:u2|lpm_counter:q_rtl_0|dffs[2], block1:u2|lpm_counter:q_rtl_0|dffs[1], block1:u2|lpm_counter:q_rtl_0|dffs[0] ; q[12] ;
; A ; LC11 ; block1:u2|lpm_counter:q_rtl_0|dffs[0], block1:u2|lpm_counter:q_rtl_0|dffs[2], block1:u2|lpm_counter:q_rtl_0|dffs[1] ; q[8] ;
; A ; LC3 ; block1:u2|lpm_counter:q_rtl_0|dffs[0], block1:u2|lpm_counter:q_rtl_0|dffs[2], block1:u2|lpm_counter:q_rtl_0|dffs[1] ; q[9] ;
; A ; LC13 ; block1:u2|lpm_counter:q_rtl_0|dffs[2], block1:u2|lpm_counter:q_rtl_0|dffs[0], block1:u2|lpm_counter:q_rtl_0|dffs[1] ; q[11] ;
; A ; LC14 ; block1:u2|lpm_counter:q_rtl_0|dffs[0], block1:u2|lpm_counter:q_rtl_0|dffs[2], block1:u2|lpm_counter:q_rtl_0|dffs[1] ; q[13] ;
; A ; LC16 ; block1:u2|lpm_counter:q_rtl_0|dffs[1], block1:u2|lpm_counter:q_rtl_0|dffs[2], block1:u2|lpm_counter:q_rtl_0|dffs[0] ; q[14] ;
; B ; LC19 ; jishi:u1|lpm_counter:q_rtl_1|dffs[2], jishi:u1|lpm_counter:q_rtl_1|dffs[0], jishi:u1|lpm_counter:q_rtl_1|dffs[3], jishi:u1|lpm_counter:q_rtl_1|dffs[1] ; q[5] ;
; B ; LC21 ; jishi:u1|lpm_counter:q_rtl_1|dffs[0], jishi:u1|lpm_counter:q_rtl_1|dffs[3], jishi:u1|lpm_counter:q_rtl_1|dffs[1], jishi:u1|lpm_counter:q_rtl_1|dffs[2] ; q[6] ;
; B ; LC24 ; jishi:u1|lpm_counter:q_rtl_1|dffs[3], jishi:u1|lpm_counter:q_rtl_1|dffs[1], jishi:u1|lpm_counter:q_rtl_1|dffs[2], jishi:u1|lpm_counter:q_rtl_1|dffs[0] ; q[4] ;
; B ; LC25 ; jishi:u1|lpm_counter:q_rtl_1|dffs[0], jishi:u1|lpm_counter:q_rtl_1|dffs[1], jishi:u1|lpm_counter:q_rtl_1|dffs[2], jishi:u1|lpm_counter:q_rtl_1|dffs[3] ; q[0] ;
; B ; LC17 ; jishi:u1|lpm_counter:q_rtl_1|dffs[1], jishi:u1|lpm_counter:q_rtl_1|dffs[3], jishi:u1|lpm_counter:q_rtl_1|dffs[2], jishi:u1|lpm_counter:q_rtl_1|dffs[0] ; q[3] ;
; B ; LC27 ; jishi:u1|lpm_counter:q_rtl_1|dffs[2], jishi:u1|lpm_counter:q_rtl_1|dffs[0], jishi:u1|lpm_counter:q_rtl_1|dffs[1], jishi:u1|lpm_counter:q_rtl_1|dffs[3] ; q[1] ;
; B ; LC29 ; jishi:u1|lpm_counter:q_rtl_1|dffs[2], jishi:u1|lpm_counter:q_rtl_1|dffs[1], jishi:u1|lpm_counter:q_rtl_1|dffs[3], jishi:u1|lpm_counter:q_rtl_1|dffs[0] ; q[2] ;
; C ; LC35 ; ; q[7] ;
; C ; LC37 ; ; q[15] ;
+-----+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+-----------------------------------------+
; Option ; Setting ;
+----------------------------------------------+-----------------------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As output driving an unspecified signal ;
; Security bit ; Off ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+-----------------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Wed May 06 13:18:36 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off jishu60 -c jishu60
Info: Selected device EPM7128SLC84-10 for design "jishu60"
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Wed May 06 13:18:36 2009
Info: Elapsed time: 00:00:00
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