jishi.v

来自「verilog实例」· Verilog 代码 · 共 15 行

module jishi(clk,clr,ena,cout,q);
   	input 		clk,clr,ena;
   	output [3:0] 	q;
	output	cout;
  	reg  [3:0] 	q;
reg cout1;
always @(posedge clr or posedge clk)
	begin
		 if (clr)	q =4'b0000;
		else if ((ena==1)&&(q<4'b1001))	q = q+1;
		else q=0;
		     end
  	assign cout=q[0]&(~q[1])&(~q[2])&q[3]; 
endmodule