jishu60.tan.rpt

verilog实例

+------------------------------------------------------------------------------------------------+
; tco                                                                                            ;
+-------+--------------+------------+---------------------------------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From                                  ; To    ; From Clock ;
+-------+--------------+------------+---------------------------------------+-------+------------+
; N/A   ; None         ; 13.000 ns  ; block1:u2|lpm_counter:q_rtl_0|dffs[1] ; q[14] ; clk        ;
; N/A   ; None         ; 13.000 ns  ; block1:u2|lpm_counter:q_rtl_0|dffs[2] ; q[14] ; clk        ;
; N/A   ; None         ; 13.000 ns  ; block1:u2|lpm_counter:q_rtl_0|dffs[0] ; q[14] ; clk        ;
; N/A   ; None         ; 13.000 ns  ; block1:u2|lpm_counter:q_rtl_0|dffs[1] ; q[13] ; clk        ;
; N/A   ; None         ; 13.000 ns  ; block1:u2|lpm_counter:q_rtl_0|dffs[2] ; q[13] ; clk        ;
; N/A   ; None         ; 13.000 ns  ; block1:u2|lpm_counter:q_rtl_0|dffs[0] ; q[13] ; clk        ;
; N/A   ; None         ; 13.000 ns  ; block1:u2|lpm_counter:q_rtl_0|dffs[1] ; q[11] ; clk        ;
; N/A   ; None         ; 13.000 ns  ; block1:u2|lpm_counter:q_rtl_0|dffs[2] ; q[11] ; clk        ;
; N/A   ; None         ; 13.000 ns  ; block1:u2|lpm_counter:q_rtl_0|dffs[0] ; q[11] ; clk        ;
; N/A   ; None         ; 13.000 ns  ; block1:u2|lpm_counter:q_rtl_0|dffs[1] ; q[9]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; block1:u2|lpm_counter:q_rtl_0|dffs[2] ; q[9]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; block1:u2|lpm_counter:q_rtl_0|dffs[0] ; q[9]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; block1:u2|lpm_counter:q_rtl_0|dffs[1] ; q[8]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; block1:u2|lpm_counter:q_rtl_0|dffs[2] ; q[8]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; block1:u2|lpm_counter:q_rtl_0|dffs[0] ; q[8]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[0]  ; q[2]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[3]  ; q[2]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[1]  ; q[2]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[2]  ; q[2]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; block1:u2|lpm_counter:q_rtl_0|dffs[1] ; q[12] ; clk        ;
; N/A   ; None         ; 13.000 ns  ; block1:u2|lpm_counter:q_rtl_0|dffs[2] ; q[12] ; clk        ;
; N/A   ; None         ; 13.000 ns  ; block1:u2|lpm_counter:q_rtl_0|dffs[0] ; q[12] ; clk        ;
; N/A   ; None         ; 13.000 ns  ; block1:u2|lpm_counter:q_rtl_0|dffs[1] ; q[10] ; clk        ;
; N/A   ; None         ; 13.000 ns  ; block1:u2|lpm_counter:q_rtl_0|dffs[2] ; q[10] ; clk        ;
; N/A   ; None         ; 13.000 ns  ; block1:u2|lpm_counter:q_rtl_0|dffs[0] ; q[10] ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[0]  ; q[3]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[3]  ; q[3]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[1]  ; q[3]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[2]  ; q[3]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[0]  ; q[1]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[3]  ; q[1]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[1]  ; q[1]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[2]  ; q[1]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[0]  ; q[0]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[3]  ; q[0]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[1]  ; q[0]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[2]  ; q[0]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; block1:u2|lpm_counter:q_rtl_0|dffs[1] ; cout  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; block1:u2|lpm_counter:q_rtl_0|dffs[2] ; cout  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; block1:u2|lpm_counter:q_rtl_0|dffs[0] ; cout  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[0]  ; q[6]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[3]  ; q[6]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[1]  ; q[6]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[2]  ; q[6]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[0]  ; q[5]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[3]  ; q[5]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[1]  ; q[5]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[2]  ; q[5]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[0]  ; q[4]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[3]  ; q[4]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[1]  ; q[4]  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; jishi:u1|lpm_counter:q_rtl_1|dffs[2]  ; q[4]  ; clk        ;
+-------+--------------+------------+---------------------------------------+-------+------------+


+--------------------------------------------------------------------------------------------------+
; th                                                                                               ;
+---------------+-------------+-----------+------+--------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                                   ; To Clock ;
+---------------+-------------+-----------+------+--------------------------------------+----------+
; N/A           ; None        ; -2.000 ns ; ena  ; jishi:u1|lpm_counter:q_rtl_1|dffs[0] ; clk      ;
; N/A           ; None        ; -2.000 ns ; ena  ; jishi:u1|lpm_counter:q_rtl_1|dffs[3] ; clk      ;
; N/A           ; None        ; -2.000 ns ; ena  ; jishi:u1|lpm_counter:q_rtl_1|dffs[1] ; clk      ;
; N/A           ; None        ; -2.000 ns ; ena  ; jishi:u1|lpm_counter:q_rtl_1|dffs[2] ; clk      ;
+---------------+-------------+-----------+------+--------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed May 06 13:18:40 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off jishu60 -c jishu60
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 100.0 MHz between source register "jishi:u1|lpm_counter:q_rtl_1|dffs[0]" and destination register "jishi:u1|lpm_counter:q_rtl_1|dffs[0]" (period= 10.0 ns)
    Info: + Longest register to register delay is 6.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 35; REG Node = 'jishi:u1|lpm_counter:q_rtl_1|dffs[0]'
        Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC2; Fanout = 35; REG Node = 'jishi:u1|lpm_counter:q_rtl_1|dffs[0]'
        Info: Total cell delay = 5.000 ns ( 83.33 % )
        Info: Total interconnect delay = 1.000 ns ( 16.67 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 7; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2; Fanout = 35; REG Node = 'jishi:u1|lpm_counter:q_rtl_1|dffs[0]'
            Info: Total cell delay = 1.500 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 7; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2; Fanout = 35; REG Node = 'jishi:u1|lpm_counter:q_rtl_1|dffs[0]'
            Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 2.000 ns
    Info: + Micro setup delay of destination is 2.000 ns
Info: tsu for register "jishi:u1|lpm_counter:q_rtl_1|dffs[0]" (data pin = "ena", clock pin = "clk") is 7.000 ns
    Info: + Longest pin to register delay is 6.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_52; Fanout = 9; PIN Node = 'ena'
        Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC2; Fanout = 35; REG Node = 'jishi:u1|lpm_counter:q_rtl_1|dffs[0]'
        Info: Total cell delay = 5.500 ns ( 84.62 % )
        Info: Total interconnect delay = 1.000 ns ( 15.38 % )
    Info: + Micro setup delay of destination is 2.000 ns
    Info: - Shortest clock path from clock "clk" to destination register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 7; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2; Fanout = 35; REG Node = 'jishi:u1|lpm_counter:q_rtl_1|dffs[0]'
        Info: Total cell delay = 1.500 ns ( 100.00 % )
Info: tco from clock "clk" to destination pin "q[14]" through register "block1:u2|lpm_counter:q_rtl_0|dffs[1]" is 13.000 ns
    Info: + Longest clock path from clock "clk" to source register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 7; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC9; Fanout = 19; REG Node = 'block1:u2|lpm_counter:q_rtl_0|dffs[1]'
        Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 2.000 ns
    Info: + Longest register to pin delay is 9.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC9; Fanout = 19; REG Node = 'block1:u2|lpm_counter:q_rtl_0|dffs[1]'
        Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.000 ns; Loc. = LC16; Fanout = 1; COMB Node = 'Dec7s:u4|WideOr0~87'
        Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 9.500 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'q[14]'
        Info: Total cell delay = 8.500 ns ( 89.47 % )
        Info: Total interconnect delay = 1.000 ns ( 10.53 % )
Info: th for register "jishi:u1|lpm_counter:q_rtl_1|dffs[0]" (data pin = "ena", clock pin = "clk") is -2.000 ns
    Info: + Longest clock path from clock "clk" to destination register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 7; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2; Fanout = 35; REG Node = 'jishi:u1|lpm_counter:q_rtl_1|dffs[0]'
        Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 3.000 ns
    Info: - Shortest pin to register delay is 6.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_52; Fanout = 9; PIN Node = 'ena'
        Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC2; Fanout = 35; REG Node = 'jishi:u1|lpm_counter:q_rtl_1|dffs[0]'
        Info: Total cell delay = 5.500 ns ( 84.62 % )
        Info: Total interconnect delay = 1.000 ns ( 15.38 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Wed May 06 13:18:40 2009
    Info: Elapsed time: 00:00:01