📄 coregen.prj
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#COREGen Project File#Wed Oct 13 06:48:38 CEST 2004overwritefiles=Trueblkmemsp_v5_0|Xilinx,\ Inc.|5.0=truedecode_8b10b_v5_0|Xilinx,\ Inc.|5.0=trueC_REG_FD_V6_0|Xilinx,\ Inc.|6.0=trueC_MUX_BIT_V5_0|Xilinx,\ Inc.|5.0=falseC_REG_FD_V3_0|Xilinx,\ Inc.|3.0=falseconvolution_v2_0|Xilinx,\ Inc.|2.0=falseC_TWOS_COMP_V4_0|Xilinx,\ Inc.|4.0=falseC_SHIFT_FD_V6_0|Xilinx,\ Inc.|6.0=trueC_DDS_V4_2|Xilinx,\ Inc.|4.2=truexlnx_PCI32sII|Xilinx,\ Inc.|3.0=trueC_ACCUM_V5_0|Xilinx,\ Inc.|5.0=falseC_GATE_BIT_BUS_V6_0|Xilinx,\ Inc.|6.0=trueC_GATE_BIT_BUS_V3_0|Xilinx,\ Inc.|3.0=falsexlnx_pci_express_x1|Xilinx,\ Inc.|1.0=truexilinxfamily=Virtex2C_DIST_MEM_V4_1|Xilinx,\ Inc.|4.1=falseC_COUNTER_BINARY_V5_0|Xilinx,\ Inc.|5.0=falseC_COUNTER_BINARY_V2_0|Xilinx,\ Inc.|2.0=falseC_ADDSUB_V4_0|Xilinx,\ Inc.|4.0=falseoutputoption=DesignFlowC_MUX_SLICE_BUFE_V2_0|Xilinx,\ Inc.|2.0=falsedividervht|Xilinx,\ Inc.|2.0=trueC_GATE_BIT_V4_0|Xilinx,\ Inc.|4.0=falsesimvendor=ModelSimmult_gen_v6_0|Xilinx,\ Inc.|6.0=truevfft64v2|Xilinx,\ Inc.|2.0=trueC_MUX_BUS_V2_0|Xilinx,\ Inc.|2.0=falseC_DA_FIR_V7_0|Xilinx,\ Inc.|7.0=falseC_REG_LD_V6_0|Xilinx,\ Inc.|6.0=truemac_v2_0|Xilinx,\ Inc.|2.0=trueC_REG_LD_V3_0|Xilinx,\ Inc.|3.0=falsesid_v2_0|Xilinx,\ Inc.|2.0=falseC_MUX_SLICE_BUFE_V5_0|Xilinx,\ Inc.|5.0=falseC_MUX_SLICE_BUFT_V2_0|Xilinx,\ Inc.|2.0=falseC_SHIFT_RAM_V6_0|Xilinx,\ Inc.|6.0=trueC_SHIFT_RAM_V3_0|Xilinx,\ Inc.|3.0=falseADPCM32_catalog|Xilinx,\ Inc.|1.0=trueC_MUX_BUS_V5_0|Xilinx,\ Inc.|5.0=falseoutputproducts=ImpNetlist;VHDLSimcam_v4_0|Xilinx,\ Inc.|4.0=trueC_MAC_FIR_V2_0|Xilinx,\ Inc.|2.0=falseC_COMPARE_V4_0|Xilinx,\ Inc.|4.0=falseC_DA_2D_DCT_V2_0|Xilinx,\ Inc.|2.0=trueC_BIT_CORRELATOR_V3_0|Xilinx,\ Inc.|3.0=truecordic_v2_0|Xilinx,\ Inc.|2.0=truexlnx_PCI64v|Xilinx,\ Inc.|3.0=truefileversion=4viterbi_v3_0|Xilinx,\ Inc.|3.0=truedecode_8b10b_v4_0|Xilinx,\ Inc.|4.0=falseC_DIST_MEM_V3_0|Xilinx,\ Inc.|3.0=falseC_MUX_SLICE_BUFT_V5_0|Xilinx,\ Inc.|5.0=falseC_REG_FD_V2_0|Xilinx,\ Inc.|2.0=falseencode_8b10b_v4_0|Xilinx,\ Inc.|4.0=truexapp265|Xilinx,\ Inc.|1.1=trueC_DECODE_BINARY_V5_0|Xilinx,\ Inc.|5.0=falseC_DECODE_BINARY_V2_0|Xilinx,\ Inc.|2.0=falsers_decoder_v4_0|Xilinx,\ Inc.|4.0=trueC_SHIFT_FD_V2_0|Xilinx,\ Inc.|2.0=falseC_GATE_BUS_V4_0|Xilinx,\ Inc.|4.0=falseblkmemdp_v3_0|Xilinx,\ Inc.|3.0=falseC_MAC_V3_0|Xilinx,\ Inc.|3.0=truesync_fifo_v2_0|Xilinx,\ Inc.|2.0=falseposphyl3_link_v1_0|Xilinx,\ Inc.|1.0=trueblkmemsp_v4_0|Xilinx,\ Inc.|4.0=falseC_DIST_MEM_V6_0|Xilinx,\ Inc.|6.0=trueC_REG_FD_V5_0|Xilinx,\ Inc.|5.0=falseC_MUX_BIT_V4_0|Xilinx,\ Inc.|4.0=falseC_TWOS_COMP_V3_0|Xilinx,\ Inc.|3.0=falseC_SHIFT_FD_V5_0|Xilinx,\ Inc.|5.0=falseformalverification=NoneC_ACCUM_V4_0|Xilinx,\ Inc.|4.0=falseC_GATE_BIT_BUS_V5_0|Xilinx,\ Inc.|5.0=falseC_GATE_BIT_BUS_V2_0|Xilinx,\ Inc.|2.0=falseC_COUNTER_BINARY_V4_0|Xilinx,\ Inc.|4.0=falsevfft1024|Xilinx,\ Inc.|1.0=trueC_ADDSUB_V3_0|Xilinx,\ Inc.|3.0=falsevfft1024v2|Xilinx,\ Inc.|2.0=trueC_MUX_SLICE_BUFE_V4_0|Xilinx,\ Inc.|4.0=falseC_SHIFT_RAM_V2_0|Xilinx,\ Inc.|2.0=falsexfft_v2_0|Xilinx,\ Inc.|2.0=truedesignflow=VHDLC_GATE_BIT_V3_0|Xilinx,\ Inc.|3.0=falsemult_gen_v5_0|Xilinx,\ Inc.|5.0=falseC_TWOS_COMP_V6_0|Xilinx,\ Inc.|6.0=truexlnx_pci64_dk|Xilinx,\ Inc.|1.0=truevfft64|Xilinx,\ Inc.|1.0=trueC_DDC_V1_0|Xilinx,\ Inc.|1.0=trueC_DA_FIR_V6_0|Xilinx,\ Inc.|6.0=falseC_REG_LD_V5_0|Xilinx,\ Inc.|5.0=falseC_REG_LD_V2_0|Xilinx,\ Inc.|2.0=falseC_ADDSUB_V6_0|Xilinx,\ Inc.|6.0=truelockedprops=lfsr_v3_0|Xilinx,\ Inc.|3.0=trueC_CIC_V3_0|Xilinx,\ Inc.|3.0=trueC_SHIFT_RAM_V5_0|Xilinx,\ Inc.|5.0=falseasync_fifo_v5_0|Xilinx,\ Inc.|5.0=falseblkmemdp_v3_2|Xilinx,\ Inc.|3.2=falseC_GATE_BIT_V6_0|Xilinx,\ Inc.|6.0=truesimulationoutputproducts=VHDLC_MUX_BUS_V4_0|Xilinx,\ Inc.|4.0=falseC_SIN_COS_V4_0|Xilinx,\ Inc.|4.0=falseHDLC32_catalog|Xilinx,\ Inc.|1.0=truebusformat=BusFormatAngleBracketNotRippedcam_v3_0|Xilinx,\ Inc.|3.0=falsevfft256v2|Xilinx,\ Inc.|2.0=trueC_MAC_FIR_V1_0|Xilinx,\ Inc.|1.0=falseC_COMPARE_V3_0|Xilinx,\ Inc.|3.0=falsevfft16|Xilinx,\ Inc.|1.0=truexlnx_PCI64s2|Xilinx,\ Inc.|3.0=truecordic_v1_0|Xilinx,\ Inc.|1.0=falseflowvendor=Othermagicnumber=-1172307782C_DIST_MEM_V2_0|Xilinx,\ Inc.|2.0=falseviterbi_v2_0|Xilinx,\ Inc.|2.0=falseC_MUX_SLICE_BUFT_V4_0|Xilinx,\ Inc.|4.0=falseencode_8b10b_v3_0|Xilinx,\ Inc.|3.0=falseC_SIN_COS_V4_1|Xilinx,\ Inc.|4.1=falseHDLC1_catalog|Xilinx,\ Inc.|1.0=trueC_DECODE_BINARY_V4_0|Xilinx,\ Inc.|4.0=falsers_decoder_v3_0|Xilinx,\ Inc.|3.0=falsers_encoder_v4_0|Xilinx,\ Inc.|4.0=trueC_GATE_BUS_V3_0|Xilinx,\ Inc.|3.0=falseblkmemdp_v5_0|Xilinx,\ Inc.|5.0=truesync_fifo_v4_0|Xilinx,\ Inc.|4.0=truesync_fifo_v1_0|Xilinx,\ Inc.|1.0=falseC_ACCUM_V3_0|Xilinx,\ Inc.|3.0=falseC_COMPARE_V6_0|Xilinx,\ Inc.|6.0=truecordic_v1_1|Xilinx,\ Inc.|1.1=falseblkmemsp_v3_0|Xilinx,\ Inc.|3.0=falseasync_fifo_v5_1|Xilinx,\ Inc.|5.1=trueC_DIST_MEM_V5_0|Xilinx,\ Inc.|5.0=falseC_MUX_BIT_V6_0|Xilinx,\ Inc.|6.0=trueC_REG_FD_V4_0|Xilinx,\ Inc.|4.0=falseC_MUX_BIT_V3_0|Xilinx,\ Inc.|3.0=falseconvolution_v3_0|Xilinx,\ Inc.|3.0=truemult_gen_v4_0|Xilinx,\ Inc.|4.0=falsexfft1024_v1_1|Xilinx,\ Inc.|1.1=trueC_TWOS_COMP_V2_0|Xilinx,\ Inc.|2.0=falseflexbus4_v1_0|Xilinx,\ Inc.|1.0=trueC_SHIFT_FD_V4_0|Xilinx,\ Inc.|4.0=falseC_GATE_BUS_V6_0|Xilinx,\ Inc.|6.0=trueexpandedtaxonomy=\ /Memories_&_Storage_ElementsC_ACCUM_V6_0|Xilinx,\ Inc.|6.0=trueC_GATE_BIT_BUS_V4_0|Xilinx,\ Inc.|4.0=falseselectedtaxonomy=/Memories_&_Storage_Elements/RAMs_&_ROMsC_DIST_MEM_V5_1|Xilinx,\ Inc.|5.1=falseC_ADDSUB_V5_0|Xilinx,\ Inc.|5.0=falseC_COUNTER_BINARY_V3_0|Xilinx,\ Inc.|3.0=falselfsr_v2_0|Xilinx,\ Inc.|2.0=falseC_ADDSUB_V2_0|Xilinx,\ Inc.|2.0=falseC_MUX_SLICE_BUFE_V3_0|Xilinx,\ Inc.|3.0=falseC_SIN_COS_V4_2|Xilinx,\ Inc.|4.2=truevfft16v2|Xilinx,\ Inc.|2.0=truexlnx_PCIX64_virtex_e_ii|Xilinx,\ Inc.|5.0=trueC_GATE_BIT_V5_0|Xilinx,\ Inc.|5.0=falseC_GATE_BIT_V2_0|Xilinx,\ Inc.|2.0=falseC_MUX_BUS_V3_0|Xilinx,\ Inc.|3.0=falseC_TWOS_COMP_V5_0|Xilinx,\ Inc.|5.0=falseC_DA_FIR_V8_0|Xilinx,\ Inc.|8.0=trueC_DA_FIR_V5_0|Xilinx,\ Inc.|5.0=falseC_DDS_V4_0|Xilinx,\ Inc.|4.0=falseC_REG_LD_V4_0|Xilinx,\ Inc.|4.0=falseC_COUNTER_BINARY_V6_0|Xilinx,\ Inc.|6.0=trueC_DA_1D_DCT_V2_1|Xilinx,\ Inc.|2.1=trueC_MUX_SLICE_BUFE_V6_0|Xilinx,\ Inc.|6.0=trueC_SHIFT_RAM_V4_0|Xilinx,\ Inc.|4.0=falseasync_fifo_v4_0|Xilinx,\ Inc.|4.0=falsexlnx_PCI32v|Xilinx,\ Inc.|3.0=truevfft32_v3_0|Xilinx,\ Inc.|3.0=truetaxonomymode=1C_MUX_BUS_V6_0|Xilinx,\ Inc.|6.0=trueblkmemsp_v3_2|Xilinx,\ Inc.|3.2=falseC_COMPARE_V2_0|Xilinx,\ Inc.|2.0=falseC_DDS_V4_1|Xilinx,\ Inc.|4.1=falsevfft256|Xilinx,\ Inc.|1.0=truesimelaboptions=C_DIST_MEM_V4_0|Xilinx,\ Inc.|4.0=falseC_MUX_SLICE_BUFT_V6_0|Xilinx,\ Inc.|6.0=truesid_v3_0|Xilinx,\ Inc.|3.0=truexilinxsubfamily=Virtex2C_MUX_SLICE_BUFT_V3_0|Xilinx,\ Inc.|3.0=falseC_MUX_BIT_V2_0|Xilinx,\ Inc.|2.0=falseC_DECODE_BINARY_V6_0|Xilinx,\ Inc.|6.0=trueC_SHIFT_FD_V3_0|Xilinx,\ Inc.|3.0=falsecorelibraryid=0C_DECODE_BINARY_V3_0|Xilinx,\ Inc.|3.0=falsers_encoder_v3_0|Xilinx,\ Inc.|3.0=falseC_GATE_BUS_V5_0|Xilinx,\ Inc.|5.0=falseC_GATE_BUS_V2_0|Xilinx,\ Inc.|2.0=falseblkmemdp_v4_0|Xilinx,\ Inc.|4.0=falsesync_fifo_v3_0|Xilinx,\ Inc.|3.0=falseC_MAC_FIR_V3_0|Xilinx,\ Inc.|3.0=trueC_ACCUM_V2_0|Xilinx,\ Inc.|2.0=falseC_COMPARE_V5_0|Xilinx,\ Inc.|5.0=false⌨️ 快捷键说明
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