notetabs.vhd

来自「本文介绍了乐曲演奏电路的设计与实现中涉及的CPLD／FPGA可编程逻辑控件,开发」· VHDL 代码 · 共 23 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity notetabs is
	port(clk:in std_logic;
		toneindex:out std_logic_vector(3 downto 0));
end;
architecture one of notetabs is 
component music
	port(address:in std_logic_vector(7 downto 0);
		inclock:in std_logic;
		q:out std_logic_vector(3 downto 0));
	end component;
	signal counter:std_logic_vector(7 downto 0);
	begin
		cnt8:process(clk)
	begin
		if counter=138 then counter<="00000000";
		elsif (clk'event and clk='1') then counter<=counter+1;end if;
	end process;
	u1:music port map(address=>counter,q=>toneindex,inclock=>clk);
end;