songer.vhd

来自「本文介绍了乐曲演奏电路的设计与实现中涉及的CPLD／FPGA可编程逻辑控件,开发」· VHDL 代码 · 共 33 行

Library ieee;
Use ieee.std_logic_1164.all;
Entity songer is
    Port( clk12mhz : in std_logic;
          Clk8hz: in std_logic;
          Code1 :out std_logic_vector(3 downto 0) ;
          High1 : out std_logic;
          spkout : out std_logic);
End;
Architecture one of songer is
          Component notetabs
              Port( clk : in std_logic;
                    Toneindex : out std_logic_vector(3 downto 0));
           End component;
           Component tonetaba
               Port( index : in std_logic_vector(3 downto 0);
                     Code : out std_logic_vector(3 downto 0);
                     High : out std_logic;
                     Tone : out std_logic_vector(10 downto 0));
           End component;
           Component speakera
               Port(  clk : in std_logic;
                      tone : in std_logic_vector(10 downto 0);
                      spks : out std_logic );
           End component;
           Signal  tone : std_logic_vector(10 downto 0); 
           Signal  toneindex:  std_logic_vector(3 downto 0);
          Begin
U1 : notetabs port map( clk=>clk8hz,toneindex=>toneindex);
U2 : tonetaba port map( index=>toneindex,tone=>tone,code=>code1,high=>high1);
U3 : speakera port map( clk=>clk12mhz,tone=>tone,spks=>spkout);
End;