speakera.vhd

来自「本文介绍了乐曲演奏电路的设计与实现中涉及的CPLD／FPGA可编程逻辑控件,开发」· VHDL 代码 · 共 38 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity speakera is
port(clk:in std_logic;
	tone:std_logic_vector(10 downto 0);
	spks:out std_logic);
end;
architecture one of speakera is
	signal preclk,fullspks:std_logic;
begin
	divideclk:process(clk)
	variable c4:std_logic_vector(3 downto 0);
	begin
		preclk<='0';
		if c4>11 then preclk<='1';c4:="0000";
		elsif clk'event and clk='1' then c4:=c4+1;
		end if;
	end process;
	genspks:process(preclk,tone)
		variable c11:std_logic_vector(10 downto 0);
	begin
	if preclk'event and preclk='1' then 
		if c11=16#7ff# then c11:=tone;fullspks<='1';
			else c11:=c11+1;fullspks<='0';
		end if;
	end if;
	end process;
	delayspks:process(fullspks)
	variable c2:std_logic;
	begin
	if fullspks'event and fullspks='1' then c2:=not c2;
		if c2='1' then spks<='1';
		else spks<='0';end if;
	end if;
	end process;
end;